Searched +full:hart +full:- +full:indexes (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: ACLINT Supervisor-level Software Interrupt Device10 - Inochi Amaoto <inochiama@outlook.com>14 supervisor-level IPI functionality for a set of HARTs on a supported16 HART connected to the SSWI device. See draft specification17 https://github.com/riscvarchive/riscv-aclint21 - THEAD C900[all …]
1 // SPDX-License-Identifier: GPL-2.036 * riscv_get_hart_index() - get hart index for interrupt delivery38 * @logical_index: index within the "interrupts-extended" property39 * @hart_index: filled with the hart index to use41 * RISC-V uses term "hart index" for its interrupt controllers, for the43 * It may be arbitrary numbers assigned to each destination hart in context46 * These numbers encoded in the optional property "riscv,hart-indexes"47 * that should contain hart index for each interrupt destination in the same48 * order as in the "interrupts-extended" property. If this property50 * "interrupts-extended" property.[all …]
1 // SPDX-License-Identifier: GPL-2.012 #include <linux/irqchip/riscv-aplic.h>13 #include <linux/irqchip/riscv-imsic.h>21 #include "irq-riscv-aplic-main.h"43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()[all …]