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Searched full:gpll (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/clk/rockchip/
H A Dclk-rv1126.c24 gpll, enumerator
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
157 PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
158 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
159 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
160 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
161 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
167 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
[all …]
H A Dclk-rk3528.c24 apll, cpll, gpll, ppll, dpll, enumerator
36 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
118 PNAME(mux_armclk) = { "apll", "gpll" };
120 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
121 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
190 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
275 COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL,
278 COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL,
281 COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL,
284 COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL,
[all …]
H A Dclk-rv1108.c19 apll, dpll, gpll, enumerator
125 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
126 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
130 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
131 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
140 PNAME(mux_wifi_src_p) = { "gpll", "xin24m" };
141 PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" };
147 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
150 PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" };
[all …]
H A Dclk-rk3036.c21 apll, dpll, gpll, enumerator
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
127 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
142 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
175 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
186 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
200 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
454 * Make uart_pll_clk a child of the gpll, as all other sources are in rk3036_clk_init()
H A Dclk-rk3368.c17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
97 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
98 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
99 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
100 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
101 PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
103 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
105 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
106 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
120 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy_480m" };
[all …]
H A Dclk-rk3399.c19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
134 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
136 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
137 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
138 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
141 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
143 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
145 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
[all …]
H A Dclk-rk3128.c18 apll, dpll, cpll, gpll, enumerator
135 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
141 PNAME(mux_clk_peri_src_p) = { "gpll", "cpll", "gpll_div2", "gpll_div3" };
142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
144 PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
156 PNAME(mux_sclk_sfc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
[all …]
H A Dclk-rk3228.c19 apll, dpll, cpll, gpll, enumerator
141 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
142 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
143 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
144 PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
147 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
149 PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" };
175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
224 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
[all …]
H A Dclk-rk3576.c22 bpll, lpll, vpll, aupll, cpll, gpll, ppll, enumerator
284 PNAME(gpll_24m_p) = { "gpll", "xin24m" };
286 PNAME(gpll_cpll_p) = { "gpll", "cpll" };
287 PNAME(gpll_spll_p) = { "gpll", "spll" };
288 PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" };
289 PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
290 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
291 PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" };
292 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
293 PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" };
[all …]
H A Dclk-px30.c22 gpll, enumerator
142 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
145 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
147 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m"};
148 PNAME(mux_gpll_cpll_npll_p) = { "gpll", "dummy_cpll", "npll" };
149 PNAME(mux_gpll_cpll_npll_xin24m_p) = { "gpll", "dummy_cpll", "npll", "xin24m" };
150 PNAME(mux_gpll_xin24m_npll_p) = { "gpll", "xin24m", "npll"};
162 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
200 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
[all …]
H A Dclk-rk3288.c24 apll, dpll, cpll, gpll, npll, enumerator
197 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
198 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
199 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
200 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
201 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
203 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
217 PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
222 PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
[all …]
H A Dclk-rv1126b.c24 gpll, cpll, aupll, dpll enumerator
86 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
87 PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" };
88 PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" };
89 PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
91 PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" };
92 PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" };
93 PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" };
158 PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" };
161 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
[all …]
H A Dclk-rk3328.c21 apll, dpll, cpll, gpll, npll, enumerator
145 PNAME(mux_2plls_p) = { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
151 PNAME(mux_4plls_p) = { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
[all …]
H A Dclk-rk3506.c20 gpll, v0pll, v1pll, enumerator
24 * [FRAC PLL]: GPLL, V0PLL, V1PLL
109 PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" };
116 PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate"…
125 PNAME(clk_mac_ptp_root_parents_p) = { "gpll", "v0pll", "v1pll" };
128 PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voic…
138 PNAME(cclk_src_sdmmc_parents_p) = { "xin24m_gate", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
143 PNAME(clk_ref_out_parents_p) = { "xin24m", "gpll", "v0pll", "v1pll" };
155 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
177 GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL,
[all …]
H A Dclk-pll.c235 /* GPLL CON2 is not HIWORD_MASK */ in rockchip_rk3036_pll_set_params()
/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml55 - const: gpll
115 clock-names = "xin24m", "gpll";
/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
335 UNIPHIER_CLK_DIV("gpll", 4),
341 .parent_names = { "gpll/4", "ref", },
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c68 static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c,
120 /* GPLL/LPLL/DPLL/RPLL/CPLL */
246 static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c,
266 static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0);
507 "gpll-42m5", "twpll-48m",
1315 "gpll" };
H A Dsc9863a-clk.c32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
144 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x38, 3, itable,
155 &gpll.common,
184 [CLK_GPLL] = &gpll.common.hw,
548 { .hw = &gpll.common.hw },
/linux/drivers/clk/hisilicon/
H A Dclk-hi3559a.c345 HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi829 clock-names = "xin24m", "gpll";
/linux/drivers/clk/qcom/
H A Dgcc-ipq5424.c143 * There are no consumers for this GPLL in kernel yet,