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Searched full:gicv5 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5-iwb.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
21 for translating wire signals into interrupt messages to the GICv5 ITS.
H A Darm,gic-v5.yaml14 The GICv5 architecture defines the guidelines to implement GICv5
17 The GICv5 specification can be found at
20 The GICv5 architecture is composed of multiple components:
81 GICv5 has one or more Interrupt Routing Services (IRS) that are
136 GICv5 has zero or more Interrupt Translation Services (ITS) that are
177 GICv5 ITS has one or more translate register frames.
/linux/tools/testing/selftests/kvm/arm64/
H A Dno-vgic.c3 // Check that, on a GICv3-capable system (GICv3 native, or GICv5 with
5 // of the sysregs generating an UNDEF exception. Do the same for GICv5
6 // on a GICv5 host.
154 "GICv5 wrongly advertised"); in guest_code_gicv5()
157 * Try all GICv5 instructions, and fail if we don't get an UNDEF. in guest_code_gicv5()
281 "Neither GICv3 nor GICv5 supported."); in main()
294 pr_info("No GICv5 support: skipping no-vgic-v5 test\n"); in main()
H A Dvgic_v5.c728 TEST_ASSERT(!ret, "Failed to run GICv5 IRQ_LINE VM");
731 "GICv5 IRQ_LINE guest did not become ready");
744 TEST_ASSERT(!ret, "Failed to run GICv5 IRQ_LINE VM");
904 TEST_ASSERT(!ret, "GICv5 IRS_REGS save failed for %s",
918 TEST_ASSERT(!ret, "GICv5 IRS_REGS restore failed for %s",
930 TEST_FAIL("GICv5 IRS register 0x%lx was not saved", attr);
962 TEST_ASSERT(!ret && addr == (-1ULL), "GICv5 IRS returns VGIC_ADDR_UNDEF");
987 TEST_ASSERT(!ret, "GICv5 IRS base correctly set");
993 TEST_ASSERT(!ret && addr == 0, "GICv5 IRS base correctly set");
999 TEST_ASSERT(ret && errno == EEXIST, "GICv5 IR
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/linux/drivers/irqchip/
H A Dirq-gic-v5.c6 #define pr_fmt(fmt) "GICv5: " fmt
113 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_mask()
162 * Reference: I_ZLTKB/R_YRGMH GICv5 specification - section 2.9.1. in gicv5_ppi_irq_unmask()
491 * GICv5's PPIs do not have a configurable trigger or handling in gicv5_ppi_irq_set_type()
516 .name = "GICv5-PPI",
529 .name = "GICv5-SPI",
545 .name = "GICv5-LPI",
559 .name = "GICv5-IPI",
1005 "GICv5 system components present but CPU does not have FEAT_GCIE")) in gicv5_starting_cpu()
1018 "irqchip/arm/gicv5 in gicv5_smp_init()
[all...]
H A Dirq-gic-v5-its.c6 #define pr_fmt(fmt) "GICv5 ITS: " fmt
581 * We expect a GICv5 implementation requiring a large number of in gicv5_its_alloc_devtab_linear()
727 .name = "GICv5-ITS-MSI",
1190 pr_err("%pOF: unable to map GICv5 ITS_CONFIG_FRAME\n", node); in gicv5_its_init()
1245 pr_err("ITS@%pa: Unable to allocate GICv5 ITS translate domain token\n", in gic_acpi_parse_madt_its_translate()
1253 pr_err("ITS@%pa: Unable to register GICv5 ITS domain token (ITS TRANSLATE FRAME ID %d) to IORT\n", in gic_acpi_parse_madt_its_translate()
1296 if (!request_mem_region(res.start, resource_size(&res), "GICv5 ITS")) in gic_acpi_parse_madt_its()
1301 pr_err("ITS@%pa: Unable to allocate GICv5 ITS domain token\n", in gic_acpi_parse_madt_its()
H A Dirq-gic-v5-irs.c6 #define pr_fmt(fmt) "GICv5 IRS: " fmt
77 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_linear()
141 /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ in gicv5_irs_init_ist_two_level()
353 * Follow GICv5 specification recommendation to opt in for two in gicv5_irs_init_ist()
775 pr_err("%pOF: unable to map GICv5 IRS registers\n", node); in gicv5_irs_of_init()
963 r = gic_request_region(irs->config_base_address, ACPI_GICV5_IRS_MEM_SIZE, "GICv5 IRS"); in gic_acpi_parse_madt_irs()
/linux/include/linux/irqchip/
H A Darm-vgic-info.h18 /* Full GICv5, optionally with v3 compat */
41 /* GICv5 IRS base */
/linux/Documentation/arch/arm64/
H A Dbooting.rst226 For systems with a GICv5 interrupt controller to be used in v5 mode:
265 - The DT or ACPI tables must describe a GICv5 interrupt controller.
/linux/arch/arm64/kvm/vgic/
H A Dvgic-init.c193 /* Allocate a vIRS for GICv5 systems */ in kvm_vgic_create()
208 * We now know that we have a GICv5. The Arch Timer PPI in kvm_vgic_dist_init()
351 /* Register the GICv5-specific PPI ops */ in vgic_allocate_private_irqs_locked()
450 * KVM-capped) VPE table used by GICv5. in vgic_init()
H A Dvgic.c1133 * required for GICv3-on-GICv3, GICv2-on-GICv3, GICv3-on-GICv5, and the in vgic_flush_state()
/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst16 Creating a guest GICv3 device requires a host GICv3 host, or a GICv5 host with
/linux/arch/arm64/include/asm/
H A Del2_setup.h209 /* GICv5 system register access */
H A Dkvm_host.h890 /* PPI state tracking for GICv5-based guests */
H A Dsysreg.h1027 * Definitions for GICv5 instructions for the Current Domain
1093 * Definitions for GICv5 instructions for the Virtual Domain
/linux/arch/arm64/kvm/
H A Darm.c1676 /* Build a GICv5-style IntID here */ in kvm_setup_vcpu()
1694 /* Build a GICv5-style IntID here */ in __kvm_vcpu_set_target()
2694 kvm_err("NV support requires GICv3 or GICv5 with legacy support, giving up\n"); in init_pkvm_host_sve_state()
H A Dsys_regs.c730 * Note: for GICv5 the mimic the way that the num_pri_bits and in access_gicv5_idr0()
750 * For GICv5 VMs, the IAFFID value is the same as the VPE ID. The VPE ID in access_gicv5_iaffid()
5901 * On GICv5 hardware that supports FEAT_GCIE_LEGACY we can run in kvm_finalize_sys_regs()
5902 * both GICv3- and GICv5-based guests. Therefore, we initially in kvm_finalize_sys_regs()
5916 * unmodified on compatible GICv5 hosts, and avoids the inverse in kvm_finalize_sys_regs()
5917 * problem for GICv5-based guests in the future. in kvm_finalize_sys_regs()
5968 /* ...and the GICv5 system registers. */ in kvm_sys_reg_table_init()
H A Dnested.c1863 /* GICv5 is not yet supported for NV */ in kvm_vcpu_apply_reg_masks()
/linux/drivers/acpi/
H A Dbus.c1212 message = "GICv5"; in acpi_bus_init_irq()
H A Dscan.c856 "ARMH0003", /* ARM GICv5 IWB */
/linux/arch/arm64/kernel/
H A Dcpufeature.c3043 .desc = "GICv5 CPU interface",
3050 .desc = "GICv5 Legacy vCPU interface",