Searched full:gicv2 (Results 1 – 15 of 15) sorted by relevance
11 interrupt-parent = <&gicv2>;337 gicv2: interrupt-controller@7fff9000 { label522 interrupt-parent = <&gicv2>;527 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,528 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,529 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,530 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;559 interrupt-parent = <&gicv2>;564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,565 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,[all …]
17 guest GICv2 through this interface. For information on creating a guest GICv319 create both a GICv3 and GICv2 device on the same VM.58 GICv2 specs. Getting or setting such a register has the same effect as65 GICv2 is changed in a way directly observable by the guest or userspace.92 defined in the GICv2 specs. Getting or setting such a register has the96 fixed format for our implementation that fits with the model of a "GICv2112 similar to GICv2's GICH_APR.
14 possible to create both a GICv3 and GICv2 on the same VM.
4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)8 #include "foundation-v8-gicv2.dtsi"
5 * ARMv8 Foundation model DTS (GICv2 configuration)9 #include "foundation-v8-gicv2.dtsi"
4 * ARMv8 Foundation model DTS (GICv2 configuration)
14 /* Full GICv2 */27 /* GICv2 GICC VA */
20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1380 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr()392 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr()406 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr()418 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
153 seq_printf(s, "vgic_model:\t%s\n", v3 ? "GICv3" : "GICv2"); in print_dist_state()
137 * ARM_VGIC (GICv2 or GICv3) device gets created with an overlapping138 * DIST/REDIST (or DIST/CPUIF for GICv2). Assumption is 4 vcpus are going to be140 * and a DIST region is set @0x70000. The GICv2 case sets a CPUIF @0x0 and a147 struct vgic_region_attr rdist; /* CPU interface in GICv2*/ in subtest_dist_rdist()1017 print_skip("No GICv2 nor GICv3 support"); in main()
40 * more priority levels. Also note that 32 is the minimum for GICv3 and GICv2.
22 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
205 - 设备树（DT）或 ACPI 表必须描述一个 GICv2 中断控制器。
209 - 設備樹（DT）或 ACPI 表必須描述一個 GICv2 中斷控制器。
1877 * regions like the GICv2 VCPU interface can trigger uncontained in vfio_pci_core_mmap()