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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c435 if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ in program_tiling()
437 GRPH_SW_MODE, info->gfx9.swizzle, in program_tiling()
438 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), in program_tiling()
439 GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), in program_tiling()
440 GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), in program_tiling()
442 GRPH_SE_ENABLE, info->gfx9.shaderEnable); in program_tiling()
634 if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ in dce_mi_clear_tiling()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c149 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp1_program_tiling()
150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp1_program_tiling()
152 NUM_SE, log_2(info->gfx9.num_shader_engines), in hubp1_program_tiling()
153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), in hubp1_program_tiling()
154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp1_program_tiling()
157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
158 META_LINEAR, info->gfx9.meta_linear, in hubp1_program_tiling()
159 RB_ALIGNED, info->gfx9.rb_aligned, in hubp1_program_tiling()
160 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp1_program_tiling()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c68 /* On GFX9, unlike GFX10, bit TRAP_EN of SQ_SHADER_TBA_HI is in pm_map_process_v9()
267 * For GFX9.4.3, SDMA engine id can be greater than 8. in pm_map_queues_v9()
336 /* For all gfx9 ASICs > gfx941, in pm_config_dequeue_wait_counts_v9()
343 * Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU in pm_config_dequeue_wait_counts_v9()
H A Dcwsr_trap_handler_gfx9.asm25 * gfx9:
26 * cpp -DASIC_FAMILY=CHIP_VEGAM cwsr_trap_handler_gfx9.asm -P -o gfx9.sp3
27 * sp3 gfx9.sp3 -hex gfx9.hex
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c317 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp2_program_tiling()
318 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp2_program_tiling()
319 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp2_program_tiling()
322 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h434 } gfx9;/*gfx9, gfx10 and above*/ member
/linux/include/uapi/drm/
H A Ddrm_fourcc.h1654 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1660 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1661 * GFX9 as canonical version.
1732 * relevant for GFX9 and later and if the tile field is *_X/_T.
H A Damdgpu_drm.h142 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
663 /* GFX9 - GFX11: */
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm.h96 /* For GFX9 */
H A Damdgpu_amdkfd.c711 * to fix some compute applications issue on GFX9. in amdgpu_amdkfd_set_compute_idle()
H A Damdgpu_drv.c76 * - 3.15.0 - Export more gpu info for gfx9
85 * - 3.24.0 - Add high priority compute support for gfx9
87 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
H A Dgfx_v9_4_3.c2935 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ in gfx_v9_4_3_ring_get_rptr_compute()
2959 BUG(); /* only DOORBELL method supported on gfx9 now */ in gfx_v9_4_3_ring_set_wptr_compute()
4914 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs in gfx_v9_4_3_get_cu_info()
H A Damdgpu_display.c1266 "GFX9+ requires FB check based on format modifier\n"); in amdgpu_display_framebuffer_init()
H A Damdgpu_amdkfd_gpuvm.c3206 /* Those values are not set from GFX9 onwards */ in amdgpu_amdkfd_get_tile_config()
H A Damdgpu_device.c4653 /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a in amdgpu_device_init()
H A Dgfx_v11_0.c4908 * steps are necessary to avoid a DMAR error in gfx9 but it is in gfx_v11_0_hw_fini()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c404 …if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swiz… in dcn32_set_det_allocations()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_translation_helper.c929 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle; in populate_dml_surface_cfg_from_plane_state()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_pm.c1560 * NOTE: This will only work for GFX9 and newer. This file will be absent
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c7647 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN; in dm_validate_stream_and_context()