Searched full:gfx10 (Results 1 – 8 of 8) sorted by relevance
27 // GFX10.3 : Clear SGPRs, VGPRs and LDS40 asic(GFX10)
26 // GFX10.1 : Clear SGPRs, VGPRs and LDS39 asic(GFX10.1)
167 /* On gfx10, mmSDMA1_xxx registers are defined NOT based in get_sdma_rlc_reg_offset()715 * GFX10 helper for wave launch stall requirements on debug trap setting.729 * because current GFX10 chips cannot support multi-process debugging due to
418 /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ in amdgpu_gfx_mqd_sw_init()
4500 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE in gfx_v10_0_read_wave_data()8561 /* gfx10 is 32bit rptr*/ in gfx_v10_0_ring_get_rptr_gfx()8600 /* gfx10 hardware is 32bit rptr */ in gfx_v10_0_ring_get_rptr_compute()
3337 * confirmed that the APU gfx10/gfx11 needn't such update. in gfx_v9_0_cp_gfx_start()
29 * gfx10:30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp331 * sp3 gfx10.sp3 -hex gfx10.hex417 // gfx10: If there was a VALU exception, the exception state must be899 //Below part will be the save shared vgpr part (new for gfx10)1094 //Below part will be the restore shared vgpr part (new for gfx10)
1518 * dm_test_get_plane_modifiers_gfx10_1() - Verify GFX10.1 modifier list generation.1521 * Verify if a pre-10.3 NV family device dispatches to the GFX10.1 modifier1539 * dm_test_get_plane_modifiers_gfx10_3() - Verify GFX10.3 modifier list generation.1542 * Verify if a 10.3+ NV family device dispatches to the GFX10.3 modifier1665 * Verify if a GFX10-RBPLUS DCC modifier enables DCC and selects the 64B1761 * Verify if a GFX10-RBPLUS modifier with both 64B and 128B independent block1803 * Verify if a GFX10-RBPLUS modifier with only the 128B independent block bit1844 * Verify if a GFX10-RBPLUS modifier without independent block bits selects the