Searched full:gfx10 (Results 1 – 9 of 9) sorted by relevance
27 // GFX10.3 : Clear SGPRs, VGPRs and LDS40 asic(GFX10)
26 // GFX10.1 : Clear SGPRs, VGPRs and LDS39 asic(GFX10.1)
167 /* On gfx10, mmSDMA1_xxx registers are defined NOT based in get_sdma_rlc_reg_offset()715 * GFX10 helper for wave launch stall requirements on debug trap setting.729 * because current GFX10 chips cannot support multi-process debugging due to
113 /* gfx10 */
392 /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ in amdgpu_gfx_mqd_sw_init()
122 * - 3.57.0 - Compute tunneling on GFX10+
3336 * confirmed that the APU gfx10/gfx11 needn't such update. in gfx_v9_0_cp_gfx_start()
29 * gfx10:30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp331 * sp3 gfx10.sp3 -hex gfx10.hex417 // gfx10: If there was a VALU exception, the exception state must be899 //Below part will be the save shared vgpr part (new for gfx10)1094 //Below part will be the restore shared vgpr part (new for gfx10)
1670 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical1676 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has