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/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dreg_addr_bb.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
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H A Dreg_addr_e5.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
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H A Dreg_addr_k2.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
82 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
85 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
86 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
87 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
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H A Dreg_addr_ah_compile15.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
79 …memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX Chi…
82 … 0x003824UL //Access:R DataWidth:0x20 tx number of tlp sent …
85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s…
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H A Dreg_addr.h9 * or http://opensource.org/licenses/CDDL-1.0.
23 * Copyright 2014-2017 Cavium, Inc.
30 * at http://opensource.org/licenses/CDDL-1.0
80 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
83 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
86 …h:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync …
87 …taWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo pu…
88 …x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync f…
90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
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/illumos-gate/usr/src/uts/common/io/vr/
H A Dvr.c61 * (TX) and one for receive (RX).
71 * Each transmit descriptor has a DMA buffer attached to it. The data of TX
125 1, /* min effective DMA size */
126 0xFFFFFFFF, /* max DMA xfer size */
128 1, /* s/g list length */
146 1, /* min effective DMA size */
147 0xFFFFFFFF, /* max DMA xfer size */
149 1, /* s/g list length */
193 "VIA VT6102-A Rhine II Fast Ethernet",
199 "VIA VT6102-C Rhine II Fast Ethernet",
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32
5 …0x8 Description: SPA Done FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; P…
6 … Description: SPA Done FIFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; …
9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
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/illumos-gate/usr/src/uts/common/io/fibre-channel/fca/qlge/
H A Dqlge.c76 * TX dma maping handlers allow multiple sscatter-gather lists
83 QL_DMA_ADDRESS_ALIGNMENT, /* DMA address alignment, default - 8 */
85 QL_DMA_MIN_XFER_SIZE, /* min effective DMA size */
86 QL_DMA_MAX_XFER_SIZE, /* max DMA xfer size */
88 QL_MAX_TX_DMA_HANDLES, /* s/g list length */
94 * Receive buffers and Request/Response queues do not allow scatter-gather lists
101 QL_DMA_ADDRESS_ALIGNMENT, /* DMA address alignment, default - 8 */
103 QL_DMA_MIN_XFER_SIZE, /* min effective DMA size */
104 QL_DMA_MAX_XFER_SIZE, /* max DMA xfer size */
106 1, /* s/g list length, i.e no sg list */
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c44 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
83 #define OFFSETOF(_s, _m) ((u32) ((u8 *)(&((_s *) 0)->_m) - \
148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \
167 (SHMEM2_RD(cb, shmem2_base, size) > \
329 (_phy)->def_md_devad, \
335 (_phy)->def_md_devad, \
365 * elink_check_lfa - This function checks if link reinitialization is required,
378 struct elink_dev *cb = params->cb; in elink_check_lfa()
381 REG_RD(cb, params->lfa_base + in elink_check_lfa()
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/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_peu_hw.h230 * Master Data Parity Error - set if all the following conditions
234 * Fast Back-to-Back Capable (N/A in PCIE)
236 * Capabilities List - presence of extended capability item.
239 * Fast Back-to-Back Enable (N/A in PCIE)
244 * The device can issue Memory Write-and-Invalidate commands (N/A
342 * BIST, Header Type, Latency Timer, and Cache Line Size
346 * Multi-Function Device: dbi writeable
349 * Cache line size for legacy compatibility (N/A in PCIE)
374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0
432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX
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/illumos-gate/usr/src/data/hwdata/
H A Dpci.ids5 # Date: 2025-01-27 03:15:01
8 # the PCI ID Project at https://pci-ids.ucw.cz/.
14 # (version 2 or higher) or the 3-clause BSD License.
25 # device device_name <-- single tab
26 # subvendor subdevice subsystem_name <-- two tabs
30 # This is a relabelled RTL-8139
31 8139 AT-2500TX V3 Ethernet
41 7a09 PCI-to-PCI Bridge
51 7a19 PCI-to-PCI Bridge
57 7a29 PCI-to-PCI Bridge
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/illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/emlxs/
H A Dfw_lp10000.h2 * Copyright (c) 2004-2011 Emulex. All rights reserved.
14 #define emlxs_lp10000_label "LP10000-S: v1.92a1 (td192a1.all)"
588 /* 0x01190 */ 0x00, 0x00, 0x26, 0x66, 0x00, 0x00, 0x26, 0x67, /* ..&f..&g */
600 /* 0x011F0 */ 0xEA, 0x00, 0x0E, 0xB3, 0xEA, 0x00, 0x0F, 0x2D, /* .......- */
651 /* 0x01388 */ 0xEA, 0x00, 0x08, 0xF5, 0xEA, 0x00, 0x2D, 0x63, /* ......-c */
652 /* 0x01390 */ 0xEA, 0x00, 0x2D, 0xBB, 0xEA, 0x00, 0x2E, 0xAE, /* ..-..... */
659 /* 0x013C8 */ 0x01, 0xA0, 0xF0, 0x0E, 0xE5, 0x2D, 0xE0, 0x04, /* .....-.. */
660 /* 0x013D0 */ 0xE9, 0x2D, 0x5F, 0xFF, 0xE1, 0x0F, 0x20, 0x00, /* .-_..... */
661 /* 0x013D8 */ 0xE1, 0x4F, 0x30, 0x00, 0xE9, 0x2D, 0x00, 0x0C, /* .O0..-.. */
672 /* 0x01430 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x07, 0xF3, /* .-B..... */
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H A Dfw_lpe11000.h2 * Copyright (c) 2004-2011 Emulex. All rights reserved.
14 #define emlxs_lpe11000_label "LPe11000-S: v2.82a4 (zd282a4.all)"
651 /* 0x01388 */ 0xEA, 0x00, 0x09, 0x47, 0xEA, 0x00, 0x2E, 0x7F, /* ...G.... */
654 /* 0x013A0 */ 0xEA, 0x00, 0x31, 0x67, 0xEA, 0x00, 0x34, 0xDF, /* ..1g..4. */
659 /* 0x013C8 */ 0x01, 0xA0, 0xF0, 0x0E, 0xE5, 0x2D, 0xE0, 0x04, /* .....-.. */
660 /* 0x013D0 */ 0xE9, 0x2D, 0x5F, 0xFF, 0xE1, 0x0F, 0x20, 0x00, /* .-_..... */
661 /* 0x013D8 */ 0xE1, 0x4F, 0x30, 0x00, 0xE9, 0x2D, 0x00, 0x0C, /* .O0..-.. */
673 /* 0x01438 */ 0xE1, 0xB0, 0xF0, 0x0E, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
695 /* 0x014E8 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x07, 0xF9, /* .-B..... */
709 /* 0x01558 */ 0xE3, 0xA0, 0x00, 0x00, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
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H A Dfw_lpe11002.h2 * Copyright (c) 2004-2011 Emulex. All rights reserved.
14 #define emlxs_lpe11002_label "LPe11002-S: v2.82a4 (zf282a4.all)"
651 /* 0x01388 */ 0xEA, 0x00, 0x09, 0x47, 0xEA, 0x00, 0x2E, 0x7F, /* ...G.... */
654 /* 0x013A0 */ 0xEA, 0x00, 0x31, 0x67, 0xEA, 0x00, 0x34, 0xDF, /* ..1g..4. */
659 /* 0x013C8 */ 0x01, 0xA0, 0xF0, 0x0E, 0xE5, 0x2D, 0xE0, 0x04, /* .....-.. */
660 /* 0x013D0 */ 0xE9, 0x2D, 0x5F, 0xFF, 0xE1, 0x0F, 0x20, 0x00, /* .-_..... */
661 /* 0x013D8 */ 0xE1, 0x4F, 0x30, 0x00, 0xE9, 0x2D, 0x00, 0x0C, /* .O0..-.. */
673 /* 0x01438 */ 0xE1, 0xB0, 0xF0, 0x0E, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
695 /* 0x014E8 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x07, 0xF9, /* .-B..... */
709 /* 0x01558 */ 0xE3, 0xA0, 0x00, 0x00, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
[all …]
H A Dfw_lp11000.h2 * Copyright (c) 2004-2011 Emulex. All rights reserved.
14 #define emlxs_lp11000_label "LP11000-S: v2.82a4 (bd282a4.all)"
590 /* 0x011A0 */ 0x00, 0x00, 0x27, 0x66, 0x00, 0x00, 0x27, 0x67, /* ..'f..'g */
659 /* 0x013C8 */ 0x01, 0xA0, 0xF0, 0x0E, 0xE5, 0x2D, 0xE0, 0x04, /* .....-.. */
660 /* 0x013D0 */ 0xE9, 0x2D, 0x5F, 0xFF, 0xE1, 0x0F, 0x20, 0x00, /* .-_..... */
661 /* 0x013D8 */ 0xE1, 0x4F, 0x30, 0x00, 0xE9, 0x2D, 0x00, 0x0C, /* .O0..-.. */
673 /* 0x01438 */ 0xE1, 0xB0, 0xF0, 0x0E, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
695 /* 0x014E8 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x08, 0x11, /* .-B..... */
709 /* 0x01558 */ 0xE3, 0xA0, 0x00, 0x00, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
725 /* 0x015D8 */ 0xEA, 0xFF, 0xFF, 0xBB, 0xE9, 0x2D, 0x40, 0x30, /* .....-@0 */
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H A Dfw_lp11002.h2 * Copyright (c) 2004-2011 Emulex. All rights reserved.
14 #define emlxs_lp11002_label "LP11002-S: v2.82a4 (bf282a4.all)"
590 /* 0x011A0 */ 0x00, 0x00, 0x27, 0x66, 0x00, 0x00, 0x27, 0x67, /* ..'f..'g */
659 /* 0x013C8 */ 0x01, 0xA0, 0xF0, 0x0E, 0xE5, 0x2D, 0xE0, 0x04, /* .....-.. */
660 /* 0x013D0 */ 0xE9, 0x2D, 0x5F, 0xFF, 0xE1, 0x0F, 0x20, 0x00, /* .-_..... */
661 /* 0x013D8 */ 0xE1, 0x4F, 0x30, 0x00, 0xE9, 0x2D, 0x00, 0x0C, /* .O0..-.. */
673 /* 0x01438 */ 0xE1, 0xB0, 0xF0, 0x0E, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
695 /* 0x014E8 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x08, 0x11, /* .-B..... */
709 /* 0x01558 */ 0xE3, 0xA0, 0x00, 0x00, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
725 /* 0x015D8 */ 0xEA, 0xFF, 0xFF, 0xBB, 0xE9, 0x2D, 0x40, 0x30, /* .....-@0 */
[all …]
H A Dfw_lpe12000.h2 * Copyright (c) 2004-2012 Emulex. All rights reserved.
14 #define emlxs_lpe12000_label "LPe12000-S: v2.01a4 (ud201a4.all)"
255 /* 0x00728 */ 0x00, 0x00, 0x47, 0x1C, 0x00, 0x00, 0x47, 0x6C, /* ..G...Gl */
600 /* 0x011F0 */ 0xEA, 0x00, 0x0F, 0xCD, 0xEA, 0x00, 0x10, 0x47, /* .......G */
608 /* 0x01230 */ 0xEA, 0x00, 0x12, 0x2D, 0xEA, 0x00, 0x12, 0x5F, /* ...-..._ */
664 /* 0x013F0 */ 0xE5, 0x2D, 0xE0, 0x04, 0xE9, 0x2D, 0x5F, 0xFF, /* .-...-_. */
666 /* 0x01400 */ 0xE9, 0x2D, 0x00, 0x0C, 0xE3, 0x82, 0x20, 0xC0, /* .-...... */
678 /* 0x01460 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x08, 0x94, /* .-B..... */
699 /* 0x01508 */ 0xE8, 0xBD, 0xDF, 0xFF, 0xE9, 0x2D, 0x42, 0x0F, /* .....-B. */
714 /* 0x01580 */ 0xE9, 0x2D, 0x42, 0x0F, 0xEB, 0x00, 0x08, 0x4C, /* .-B....L */
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