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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi116 clocks = <&fin_pll>,
120 clock-names = "fin_pll",
130 clocks = <&fin_pll>,
134 <&fin_pll>,
143 clock-names = "fin_pll",
162 clocks = <&fin_pll>,
164 clock-names = "fin_pll",
172 clocks = <&fin_pll>,
174 clock-names = "fin_pll",
182 clocks = <&fin_pll>,
[all …]
H A Ds3c6410-smdk6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
65 clocks = <&fin_pll>;
H A Ds3c6410-mini6410.dts31 fin_pll: oscillator-0 { label
34 clock-output-names = "fin_pll";
161 clocks = <&fin_pll>;
H A Dexynos5260-xyref5260.dts30 fin_pll: xxti { label
33 clock-output-names = "fin_pll";
H A Dexynos5410.dtsi72 clocks = <&fin_pll>;
86 clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
319 clocks = <&fin_pll>, <&clock CLK_MCT>;
320 clock-names = "fin_pll", "mct";
H A Dexynos5410-smdk5410.dts30 fin_pll: xxti { label
33 clock-output-names = "fin_pll";
/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5260-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
96 - const: fin_pll
116 - const: fin_pll
145 - const: fin_pll
163 - const: fin_pll
181 - const: fin_pll
199 - const: fin_pll
216 - const: fin_pll
234 - const: fin_pll
251 - const: fin_pll
[all …]
H A Dsamsung,exynos7-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
70 - const: fin_pll
92 - const: fin_pll
113 - const: fin_pll
131 - const: fin_pll
150 - const: fin_pll
179 - const: fin_pll
197 - const: fin_pll
216 - const: fin_pll
239 - const: fin_pll
[all …]
H A Dtesla,fsd-clock.yaml59 - const: fin_pll
76 - const: fin_pll
98 - const: fin_pll
120 - const: fin_pll
139 - const: fin_pll
155 - const: fin_pll
169 - const: fin_pll
190 clocks = <&fin_pll>,
193 clock-names = "fin_pll",
H A Dsamsung,exynos5410-clock.yaml18 - "fin_pll" - PLL input clock from XXTI
33 defined using standard clock bindings with "fin_pll" clock-output-name.
54 fin_pll: osc-clock {
57 clock-output-names = "fin_pll";
65 clocks = <&fin_pll>;
H A Dsamsung,s3c6400-clock.yaml16 - "fin_pll" - PLL input clock (xtal/extclk) - required,
56 clocks = <&fin_pll>;
H A Dsamsung,exynos-audss-clock.yaml31 Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
/linux/drivers/clk/samsung/
H A Dclk-exynos7.c45 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
46 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
47 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
48 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
49 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
174 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
176 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
178 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
180 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
182 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
[all …]
H A Dclk-exynos5260.c103 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
184 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
186 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
188 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
190 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
192 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
193 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
194 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
195 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll",
197 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll",
[all …]
H A Dclk-fsd.c165 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
167 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
169 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
171 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
176 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
177 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
178 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
179 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
180 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
181 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
[all …]
H A Dclk-exynos5410.c70 PNAME(apll_p) = { "fin_pll", "fout_apll", };
71 PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
72 PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
73 PNAME(epll_p) = { "fin_pll", "fout_epll" };
74 PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
75 PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
80 PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
81 PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
83 PNAME(sclk_mpll_bpll_p) = { "sclk_mpll_bpll", "fin_pll", };
85 PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
[all …]
H A Dclk-exynos5420.c300 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
301 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
302 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
303 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
304 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
305 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
306 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
307 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
308 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
309 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
[all …]
H A Dclk-exynos5250.c173 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
176 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
178 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
179 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
181 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
182 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
183 PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
184 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
185 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
191 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
[all …]
H A Dclk-s3c64xx.c86 PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
88 PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
90 PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
93 PNAME(apll_p) = { "fin_pll", "fout_apll" };
94 PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
95 PNAME(epll_p) = { "fin_pll", "fout_epll" };
104 PNAME(clk27_p6410) = { "clk27m", "fin_pll" };
105 PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" };
106 PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
107 PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
[all …]
H A Dclk-s5pv210.c135 "fin_pll",
140 "fin_pll",
145 "fin_pll",
150 "fin_pll",
251 "fin_pll",
271 "fin_pll",
283 "fin_pll",
304 "fin_pll",
348 "fin_pll",
367 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */
[all …]
H A Dclk-exynos3250.c179 PNAME(mout_vpllsrc_p) = { "fin_pll", };
181 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
182 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
183 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
184 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
186 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
187 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
198 = { "fin_pll", "div_aclk_400_mcuisp", };
202 PNAME(mout_aclk_266_sub_p) = { "fin_pll", "div_aclk_266", };
238 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
[all …]
H A Dclk-exynos4.c283 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
284 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
285 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
286 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
287 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
339 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
357 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
358 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
359 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
1014 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi40 fin_pll: clock { label
43 clock-output-names = "fin_pll";
175 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
180 clock-names = "fin_pll", "dout_sclk_bus0_pll",
189 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
193 clock-names = "fin_pll", "dout_sclk_bus0_pll",
202 clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
203 clock-names = "fin_pll", "dout_aclk_ccore_133";
210 clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
212 clock-names = "fin_pll", "dout_aclk_peric0_66",
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi339 fin_pll: clock { label
341 clock-output-names = "fin_pll";
457 clocks = <&fin_pll>,
461 clock-names = "fin_pll",
471 clocks = <&fin_pll>;
472 clock-names = "fin_pll";
479 clocks = <&fin_pll>;
480 clock-names = "fin_pll";
492 clocks = <&fin_pll>;
493 clock-names = "fin_pll";
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml44 - const: fin_pll
168 clock-names = "fin_pll", "mct";
188 clock-names = "fin_pll", "mct";
209 clock-names = "fin_pll", "mct";
229 clock-names = "fin_pll", "mct";

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