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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
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H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos5250 SoC device tree source
8 * Samsung Exynos5250 SoC device nodes are listed in this file.
9 * Exynos5250 based board files can include this file and provide
13 * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
23 compatible = "samsung,exynos5250", "samsung,exynos5";
46 #address-cells = <1>;
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H A Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
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H A Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 cpu-map {
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,exynos5250-sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5250 SoC SATA PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 const: samsung,exynos5250-sata-phy
21 clock-names:
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H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
18 0 - UTMI+ type phy,
19 1 - PIPE3 type phy.
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H A Dsamsung,dp-video-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
17 - samsung,exynos5250-dp-video-phy
18 - samsung,exynos5420-dp-video-phy
20 "#phy-cells":
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H A Dsamsung,usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
18 0 - USB device ("device"),
19 1 - USB host ("host"),
20 2 - HSIC0 ("hsic0"),
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dsamsung-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
20 - enum:
21 - google,gs101-wdt # for Google gs101
22 - samsung,s3c2410-wdt # for S3C2410
23 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
24 - samsung,exynos5250-wdt # for Exynos5250
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/linux/drivers/soc/samsung/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o
4 obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o
5 exynos_chipid-y += exynos-chipid.o exynos-asv.o
7 obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o
9 obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
11 obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
12 exynos5250-pmu.o exynos5420-pmu.o
13 obj-$(CONFIG_EXYNOS_REGULATOR_COUPLER) += exynos-regulator-coupler.o
15 obj-$(CONFIG_SAMSUNG_PM_CHECK) += s3c-pm-check.o
H A Dexynos-pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
6 // Exynos - CPU PMU(Power Management Unit) support
8 #include <linux/arm-smccc.h>
18 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include <linux/soc/samsung/exynos-pmu.h>
21 #include "exynos-pmu.h"
52 /* Write to a protected PMU register. */
62 /* returns -EINVAL if access isn't allowed or 0 */ in tensor_sec_reg_write()
69 /* Read/Modify/Write a protected PMU register. */
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H A Dexynos5250-pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
6 // Exynos5250 - CPU PMU (Power Management Unit) support
8 #include <linux/soc/samsung/exynos-regs-pmu.h>
9 #include <linux/soc/samsung/exynos-pmu.h>
11 #include "exynos-pmu.h"
/linux/arch/arm/mach-exynos/
H A Dexynos.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
15 #include <linux/soc/samsung/exynos-regs-pmu.h>
18 #include <asm/hardware/cache-l2x0.h>
33 .id = -1,
52 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") { in exynos_sysram_init()
64 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") { in exynos_sysram_init()
80 if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid")) in exynos_fdt_map_chipid()
88 iodesc.length = be32_to_cpu(reg[1]) - 1; in exynos_fdt_map_chipid()
137 * Apparently, these SoCs are not able to wake-up from suspend using
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H A Dsuspend.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
6 // Exynos - Suspend support
8 // Based on arch/arm/mach-s3c2410/pm.c
23 #include <linux/soc/samsung/exynos-pmu.h>
24 #include <linux/soc/samsung/exynos-regs-pmu.h>
27 #include <asm/hardware/cache-l2x0.h>
36 #define REG_TABLE_END (-1U)
41 * struct exynos_wkup_irq - PMU IRQ to mask mapping
42 * @hwirq: Hardware IRQ signal of the PMU
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/linux/drivers/phy/samsung/
H A Dphy-exynos-dp-video.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/soc/samsung/exynos-regs-pmu.h>
33 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on()
34 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on()
42 /* Enable power isolation on DP-PHY */ in exynos_dp_video_phy_power_off()
43 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_off()
63 .compatible = "samsung,exynos5250-dp-video-phy",
66 .compatible = "samsung,exynos5420-dp-video-phy",
76 struct device *dev = &pdev->dev; in exynos_dp_video_phy_probe()
82 return -ENOMEM; in exynos_dp_video_phy_probe()
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H A Dphy-samsung-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "phy-samsung-usb2.h"
21 struct samsung_usb2_phy_driver *drv = inst->drv; in samsung_usb2_phy_power_on()
24 dev_dbg(drv->dev, "Request to power_on \"%s\" usb phy\n", in samsung_usb2_phy_power_on()
25 inst->cfg->label); in samsung_usb2_phy_power_on()
27 if (drv->vbus) { in samsung_usb2_phy_power_on()
28 ret = regulator_enable(drv->vbus); in samsung_usb2_phy_power_on()
33 ret = clk_prepare_enable(drv->clk); in samsung_usb2_phy_power_on()
36 ret = clk_prepare_enable(drv->ref_clk); in samsung_usb2_phy_power_on()
39 if (inst->cfg->power_on) { in samsung_usb2_phy_power_on()
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/linux/drivers/clk/samsung/
H A Dclk-exynos-clkout.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
20 #define DRV_NAME "exynos-clkout"
55 .compatible = "samsung,exynos3250-pmu",
58 .compatible = "samsung,exynos4210-pmu",
61 .compatible = "samsung,exynos4212-pmu",
64 .compatible = "samsung,exynos4412-pmu",
67 .compatible = "samsung,exynos5250-pmu",
70 .compatible = "samsung,exynos5410-pmu",
73 .compatible = "samsung,exynos5420-pmu",
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H A Dclk-exynos5250.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Common Clock Framework support for Exynos5250 SoC.
10 #include <dt-bindings/clock/exynos5250.h>
11 #include <linux/clk-provider.h>
17 #include "clk-cpu.h"
18 #include "clk-exynos5-subcmu.h"
609 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
785 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
805 hws = ctx->clk_data.hws; in exynos5250_clk_init()
863 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", in exynos5250_clk_init()
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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
79 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); in s5pv210_retention_init()
83 return ERR_PTR(-ENODEV); in s5pv210_retention_init()
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,exynos-adc-v1 # Exynos5250
17 - samsung,exynos-adc-v2
18 - samsung,exynos3250-adc
19 - samsung,exynos4212-adc # Exynos4212 and Exynos4412
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/linux/drivers/watchdog/
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #include <linux/soc/samsung/exynos-pmu.h>
80 * DOC: Quirk flags for different Samsung watchdog IP-cores
84 * sometimes requires modifying PMU registers for proper functioning, register
85 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
92 * write-only, writing any values to this register clears the interrupt, but
95 * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling
100 * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register,
105 * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE
106 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
[all …]

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