Home
last modified time | relevance | path

Searched +full:erratum +full:- +full:unknown1 (Results 1 – 3 of 3) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
[all …]
/linux/drivers/clocksource/
H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
133 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write()
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); in arch_timer_reg_write()
149 writel_relaxed((u32)val, timer->base + CNTV_CTL); in arch_timer_reg_write()
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-r-ccu.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
13 #include <dt-bindings/reset/sun8i-r-ccu.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]