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/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c396 struct i915_gem_proto_engine *engines; member
425 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_balance()
452 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { in set_proto_ctx_engines_balance()
470 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL; in set_proto_ctx_engines_balance()
471 set->engines[idx].engine = siblings[0]; in set_proto_ctx_engines_balance()
474 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED; in set_proto_ctx_engines_balance()
475 set->engines[idx].num_siblings = num_siblings; in set_proto_ctx_engines_balance()
476 set->engines[idx].siblings = siblings; in set_proto_ctx_engines_balance()
517 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_bond()
522 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) { in set_proto_ctx_engines_bond()
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/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_rc6.c194 struct intel_engine_cs *engine, **engines; in randomised_engines() local
204 engines = kmalloc_objs(*engines, n); in randomised_engines()
205 if (!engines) in randomised_engines()
210 engines[n++] = engine; in randomised_engines()
212 i915_prandom_shuffle(engines, sizeof(*engines), n, prng); in randomised_engines()
215 return engines; in randomised_engines()
221 struct intel_engine_cs **engines; in live_rc6_ctx_wa() local
230 engines = randomised_engines(gt, &prng, &count); in live_rc6_ctx_wa()
231 if (!engines) in live_rc6_ctx_wa()
235 struct intel_engine_cs *engine = engines[n]; in live_rc6_ctx_wa()
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/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt5 engines within those slaves. However, we have a facility to match devicetree
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
16 represent the FSI slaves and their slave engines. As a basic outline:
41 adding subordinate device tree nodes as children of FSI engines.
79 Each slave provides an address-space, under which the engines are accessible.
91 FSI engines (devices)
94 Engines are identified by their address under the slaves' address spaces. We
116 additional engines, but they don't necessarily need to be describe in the
/linux/Documentation/netlabel/
H A Dintroduction.rst15 is composed of three main components, the protocol engines, the communication
18 Protocol Engines
21 The protocol engines are responsible for both applying and retrieving the
25 refrain from calling the protocol engines directly, instead they should use
45 independent interface to the underlying NetLabel protocol engines. In addition
/linux/include/uapi/drm/
H A Di915_drm.h160 * Different engines serve different roles, and there may be more than one
163 * on a certain subset of engines, or for providing information about that
170 * Render engines support instructions used for 3D, Compute (GPGPU),
181 * Copy engines (also referred to as "blitters") support instructions
184 * Copy engines can perform pre-defined logical or bitwise operations
192 * Video engines (also referred to as "bit stream decode" (BSD) or
201 * Video enhancement engines (also referred to as "vebox") support
209 * Compute engines support a subset of the instructions available
210 * on render engines: compute engines support Compute (GPGPU) and
728 * value reports the support of context isolation for individual engines by
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H A Dhabanalabs_accel.h799 * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h/w engines in the asic.
854 /* Maximum buffer size for retrieving engines status */
960 * Bitmask of busy engines.
966 * Extended Bitmask of busy engines.
1146 * engines which caused the razwi, it will hold all of them.
1148 * might be common for several engines and there is no way to get the
1150 * possible engines caused this razwi. Also, there might be possibility
1599 * The engines CS is merged into the existing CS ioctls.
1600 * Use it to control engines modes.
1649 /* this holds address of array of uint32 for engines */
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/linux/tools/include/uapi/drm/
H A Di915_drm.h
/linux/drivers/gpu/drm/xe/
H A Dxe_gt_ccs_mode.c35 * assignment of compute slices to compute engines would be, in __xe_gt_apply_ccs_mode()
40 * With 2 engines (ccs0, ccs1): in __xe_gt_apply_ccs_mode()
44 * With 4 engines (ccs0, ccs1, ccs2, ccs3): in __xe_gt_apply_ccs_mode()
132 * Ensure number of engines specified is valid and there is an in ccs_mode_store()
133 * exact multiple of engines for slices. in ccs_mode_store()
137 xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", in ccs_mode_store()
197 * number of compute hardware engines to which the available compute slices
H A Dxe_gt_types.h110 * the hardware engines, programmable execution units, and GuC. Each GT has
131 * @info.engine_mask: mask of engines present on GT. Some of
215 * @ccs_mode: Number of compute engines enabled.
216 * Allows fixed mapping of available compute slices to compute engines.
262 /** @hw_engines: hardware engines on the GT */
362 /** @user_engines: engines present in GT and available to userspace */
366 * consideration only engines available to userspace
372 * number of engines available to userspace
H A Dxe_gt_sriov_pf_debugfs.c378 char engines[128]; in sched_group_engines_read() local
380 engines[0] = '\0'; in sched_group_engines_read()
385 u32 mask = groups[group].engines[guc_class]; in sched_group_engines_read()
388 strlcat(engines, hwe->name, sizeof(engines)); in sched_group_engines_read()
389 strlcat(engines, " ", sizeof(engines)); in sched_group_engines_read()
392 strlcat(engines, "\n", sizeof(engines)); in sched_group_engines_read()
395 return simple_read_from_buffer(buf, count, ppos, engines, strlen(engines)); in sched_group_engines_read()
/linux/drivers/gpu/drm/i915/
H A DKconfig.profile45 The driver sends a periodic heartbeat down all active engines to
70 certain platforms and certain engines which will be reflected in the
74 int "Preempt timeout for compute engines (ms, jiffy granularity)"
89 certain platforms and certain engines which will be reflected in the
/linux/Documentation/misc-devices/
H A Dmrvl_cn10k_dpi.rst12 mailbox logic, and a set of DMA engines & DMA command queues.
20 the DMA engines and VF device's DMA command queues. Also, driver creates
38 a pem port to which DMA engines are wired.
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c40 * DMA engines. These engines are used for compute
41 * and gfx. There are two DMA engines (SDMA0, SDMA1)
243 * cik_sdma_gfx_stop - stop the gfx async dma engines
284 * cik_sdma_rlc_stop - stop the compute async dma engines
301 * Halt or unhalt the async dma engines (CIK).
323 * cik_sdma_enable - stop the async dma engines
328 * Halt or unhalt the async dma engines (CIK).
357 * cik_sdma_gfx_resume - setup and start the async dma engines
440 * cik_sdma_rlc_resume - setup and start the async dma engines
520 * cik_sdma_resume - setup and start the async dma engines
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H A Dni_dma.c41 * Cayman and newer support two asynchronous DMA engines.
150 * cayman_dma_stop - stop the async dma engines
154 * Stop the async dma engines (cayman-SI).
179 * cayman_dma_resume - setup and start the async dma engines
264 * cayman_dma_fini - tear down the async dma engines
268 * Stop the async dma engines and free the rings (cayman-SI).
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_ucode.c40 dev_err(dev, "unsupported number of engines %d on octeontx2\n", in get_cores_bmap()
56 dev_err(dev, "No engines reserved for engine group %d\n", in get_cores_bmap()
647 "Error available %s engines %d < than requested %d\n", in check_engines_availability()
661 /* Validate if a number of requested engines are available */ in reserve_engines()
668 /* Reserve requested engines for this engine group */ in reserve_engines()
739 /* Disable all engines used by this group */ in disable_eng_grp()
803 * If mirrored group has this type of engines attached then in update_requested_engs()
805 * 1) mirrored_engs.count == engs[i].count then all engines in update_requested_engs()
809 * engines from mirrored engine group will be shared with this in update_requested_engs()
811 * 3) mirrored_engs.count < engs[i].count then all engines in update_requested_engs()
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/linux/drivers/media/platform/xilinx/
H A Dxilinx-dma.h32 * @use_count: number of DMA engines using the pipeline
33 * @stream_count: number of DMA engines currently streaming
34 * @num_dmas: number of DMA engines in the pipeline
/linux/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c292 if (dmm->engines[i].async) in omap_dmm_irq_handler()
293 release_engine(&dmm->engines[i]); in omap_dmm_irq_handler()
295 complete(&dmm->engines[i].compl); in omap_dmm_irq_handler()
473 * silently fail, leading to leaking DMM engines, which may eventually in fill()
474 * lead to deadlock if we run out of DMM engines. in fill()
753 kfree(omap_dmm->engines); in omap_dmm_remove()
887 /* alloc engines */ in omap_dmm_probe()
888 omap_dmm->engines = kzalloc_objs(*omap_dmm->engines, in omap_dmm_probe()
890 if (!omap_dmm->engines) { in omap_dmm_probe()
896 omap_dmm->engines[i].id = i; in omap_dmm_probe()
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/linux/drivers/dma/idxd/
H A Dinit.c278 engine = idxd->engines[i]; in idxd_clean_engines()
283 kfree(idxd->engines); in idxd_clean_engines()
293 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), in idxd_setup_engines()
295 if (!idxd->engines) in idxd_setup_engines()
320 idxd->engines[i] = engine; in idxd_setup_engines()
327 engine = idxd->engines[i]; in idxd_setup_engines()
332 kfree(idxd->engines); in idxd_setup_engines()
569 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); in idxd_read_caps()
844 * Save IDXD device configurations including engines, groups, wqs etc.
898 /* Free saved groups and engines */ in idxd_device_config_save()
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-hsi8 engines (APE) with cellular modem engines (CMT) in cellular
/linux/Documentation/arch/powerpc/
H A Dvas-api.rst14 unit comprises of one or more hardware engines or co-processor types
62 access to all GZIP engines in the system. The only valid operations on
79 engines (typically, one per P9 chip) there is just one
130 "Discovery of available VAS engines" section below.
168 that the application can use to copy/paste its CRB to the hardware engines.
190 Discovery of available VAS engines
/linux/arch/x86/platform/geode/
H A Dalix.c108 if (!vendor || strcmp(vendor, "PC Engines")) in alix_present_dmi()
123 const char tinybios_sig[] = "PC Engines ALIX."; in alix_init()
124 const char coreboot_sig[] = "PC Engines\0ALIX."; in alix_init()
/linux/Documentation/gpu/rfc/
H A Di915_scheduler.rst43 * Features like timeslicing / preemption / virtual engines would
104 * Export engines logical mapping
109 Export engines logical mapping
116 engines in logical order which is a new requirement compared to execlists.
/linux/Documentation/devicetree/bindings/crypto/
H A Daspeed,ast2500-hace.yaml7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
15 divided into two independently engines - Hash Engine and Crypto Engine.
/linux/drivers/dma/ppc4xx/
H A Ddma.h3 * 440SPe's DMA engines support header file
17 /* Number of DMA engines available on the controller */
100 * DMAx engines Command Descriptor Block Type
/linux/drivers/gpu/drm/i915/selftests/
H A Di915_request.c1201 * Check we can submit requests to all engines simultaneously. We in live_all_engines()
1330 * Check we can submit requests to all engines sequentially, such in live_sequential_engines()
1333 * they are running on independent engines. in live_sequential_engines()
1625 * Check we can submit requests to all engines concurrently. This in live_parallel_engines()
1852 pr_info("Completed %lu waits for %lu fences across %d engines and %d cpus\n", in live_breadcrumbs_smoketest()
3192 struct p_thread *engines; in perf_parallel_engines() local
3195 engines = kzalloc_objs(*engines, nengines); in perf_parallel_engines()
3196 if (!engines) in perf_parallel_engines()
3219 memset(&engines[idx].p, 0, sizeof(engines[idx].p)); in perf_parallel_engines()
3228 engines[idx].worker = worker; in perf_parallel_engines()
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