| /freebsd/sys/contrib/device-tree/Bindings/opp/ |
| H A D | ti-omap5-opp-supply.txt | 3 OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
9 Also, some supplies may have an associated vbb-supply which is an Adaptive Body
11 to the vdd-supply and clk when making an OPP transition. By supplying two
16 [1] Documentation/devicetree/bindings/opp/opp-v2.yaml
19 - vdd-supply: phandle to regulator controlling VDD supply
20 - vbb-supply: phandle to regulator controlling Body Bias supply
23 Required Properties for opp-supply node:
24 - compatible: Should be one of:
25 "ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
26 "ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
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| /freebsd/sys/contrib/device-tree/Bindings/nvmem/ |
| H A D | microchip,sama7g5-otpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | dra76x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cell
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| H A D | dra7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controlle
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | mt6315-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/mt6315-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
15 by different efuse settings.
19 const: mediatek,mt6315-regulator
29 "^vbuck[1-4]$":
35 regulator-compatible:
36 pattern: "^vbuck[1-4]$"
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | phy-rockchip-inno-hdmi.txt | 4 - compatible : should be one of the listed compatibles:
5 * "rockchip,rk3228-hdmi-phy",
6 * "rockchip,rk3328-hdmi-phy";
7 - reg : Address and length of the hdmi phy control register set
8 - clocks : phandle + clock specifier for the phy clocks
9 - clock-names : string, clock name, must contain "sysclk" for system
10 control and register configuration, "refoclk" for crystal-
11 oscillator reference PLL clock input and "refpclk" for pclk-
13 - #clock-cells: should be 0.
14 - clock-output-names : shall be the name for the output clock.
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| /freebsd/sys/arm/allwinner/ |
| H A D | aw_thermal.c | 1 /*-
175 return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV); in a83t_to_temp()
207 return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV); in a64_to_temp()
239 return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV)); in h3_to_temp()
245 return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL); in h3_to_reg()
275 tmp = H5_TEMP_BASE - (val * H5_TEMP_MUL); in h5_to_temp()
281 tmp = H5_TEMP_BASE_CPU - (val * H5_TEMP_MUL_CPU); in h5_to_temp()
283 tmp = H5_TEMP_BASE_GPU - (val * H5_TEMP_MUL_GPU); in h5_to_temp()
299 tmp = H5_TEMP_BASE - (val << H5_TEMP_DIV); in h5_to_reg()
303 tmp = H5_TEMP_BASE_CPU - (val << H5_TEMP_DIV); in h5_to_reg()
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| /freebsd/sys/contrib/dev/rtw88/ |
| H A D | pci.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
54 return skb->priority; in rtw_pci_get_tx_qsel()
60 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
63 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
67 val = bus_read_1((struct resource *)rtwpci->mma in rtw_pci_read8()
1587 struct rtw_efuse *efuse = &rtwdev->efuse; rtw_pci_suspend() local
1599 struct rtw_efuse *efuse = &rtwdev->efuse; rtw_pci_resume() local
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| H A D | main.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
49 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
427 /* the power index is represented by differences, which cck-1s & ht40-
2003 struct rtw_efuse efuse; global() member
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| /freebsd/sys/dev/ral/ |
| H A D | rt2860.c | 1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
21 /*-
70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
238 struct ieee80211com *ic = &sc->sc_ic; in rt2860_attach()
242 sc->sc_dev = dev; in rt2860_attach()
243 sc->sc_debug = 0; in rt2860_attach()
245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in rt2860_attach()
248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); in rt2860_attach()
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| /freebsd/sys/dev/usb/wlan/ |
| H A D | if_run.c | 1 /*-
5 * Copyright (c) 2013-2014 Kevin Lo
21 /*-
115 device_printf((_sc)->sc_dev, __VA_ARGS__); \
531 /* MCS - single stream */
541 /* MCS - 2 streams */
551 /* MCS - 3 streams */
732 if (uaa->dev_state != UAA_DEV_READY) in run_autoinst()
738 id = iface->idesc; in run_autoinst()
739 if (id == NULL || id->bInterfaceClass != UICLASS_MASS) in run_autoinst()
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300reg.h | 32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors
239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors
249 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
252 #define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt
274 #define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9)
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| /freebsd/sys/dev/qlnx/qlnxe/ |
| H A D | ecore_mcp.c | 2 * Copyright (c) 2017-2018 Cavium, Inc.
57 ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
61 ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
89 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base) in ecore_mcp_is_init()
97 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, in ecore_mcp_cmd_port_init()
101 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize, in ecore_mcp_cmd_port_init()
105 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn)); in ecore_mcp_cmd_port_init()
111 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length); in ecore_mcp_read_mb()
116 if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev)) in ecore_mcp_read_mb()
120 if (!p_hwfn->mcp_info->public_base) in ecore_mcp_read_mb()
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| H A D | reg_addr.h | 2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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