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/linux/drivers/clk/tegra/
H A Dclk-dfll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
49 #include "clk-dfll.h"
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2371-2180.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra210-p2180.dtsi"
5 #include "tegra210-p2597.dtsi"
9 compatible = "nvidia,p2371-2180", "nvidia,tegra210";
14 hvddio-pex-supply = <&vdd_1v8>;
15 dvddio-pex-supply = <&vdd_pex_1v05>;
16 vddio-pex-ctl-supply = <&vdd_1v8>;
19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
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H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
25 reserved-memory {
26 #address-cells = <2>;
27 #size-cells = <2>;
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
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