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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two
15 pins which can be assigned to either the DPAUX channel or to an I2C
18 When configured for DisplayPort AUX operation, the DPAUX controller
24 pattern: "^dpaux@[0-9a-f]+$"
29 - nvidia,tegra124-dpaux
30 - nvidia,tegra210-dpaux
31 - nvidia,tegra186-dpaux
32 - nvidia,tegra194-dpaux
35 - const: nvidia,tegra132-dpaux
[all …]
H A Dnvidia,tegra124-sor.yaml99 nvidia,dpaux:
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi2110 dpaux0: dpaux@155c0000 {
2111 compatible = "nvidia,tegra194-dpaux";
2116 clock-names = "dpaux", "parent";
2118 reset-names = "dpaux";
2124 groups = "dpaux-io";
2129 groups = "dpaux-io";
2134 groups = "dpaux-io";
2144 dpaux1: dpaux@155d0000 {
2145 compatible = "nvidia,tegra194-dpaux";
2150 clock-names = "dpaux", "parent";
[all …]
H A Dtegra210.dtsi108 dpaux1: dpaux@54040000 {
109 compatible = "nvidia,tegra210-dpaux";
114 clock-names = "dpaux", "parent";
116 reset-names = "dpaux";
121 groups = "dpaux-io";
126 groups = "dpaux-io";
131 groups = "dpaux-io";
380 dpaux: dpaux@545c0000 { label
381 compatible = "nvidia,tegra210-dpaux";
386 clock-names = "dpaux", "parent";
[all …]
H A Dtegra186.dtsi1549 dpaux1: dpaux@15040000 {
1550 compatible = "nvidia,tegra186-dpaux";
1555 clock-names = "dpaux", "parent";
1557 reset-names = "dpaux";
1563 groups = "dpaux-io";
1568 groups = "dpaux-io";
1573 groups = "dpaux-io";
1806 dpaux: dpaux@155c0000 { label
1807 compatible = "nvidia,tegra186-dpaux";
1812 clock-names = "dpaux", "parent";
[all …]
H A Dtegra210-p3541-0000.dts19 dpaux@545c0000 {
H A Dtegra186-p3509-0000+p3636-0001.dts799 dpaux@15040000 {
818 nvidia,dpaux = <&dpaux>;
834 dpaux@155c0000 {
H A Dtegra132-norrin.dts45 nvidia,dpaux = <&dpaux>;
49 dpaux: dpaux@545c0000 { label
1058 ddc-i2c-bus = <&dpaux>;
H A Dtegra132.dtsi158 dpaux: dpaux@545c0000 { label
159 compatible = "nvidia,tegra124-dpaux";
164 clock-names = "dpaux", "parent";
166 reset-names = "dpaux";
H A Dtegra194-p2972-0000.dts2197 dpaux@155c0000 {
2201 dpaux@155d0000 {
2205 dpaux@155e0000 {
2216 nvidia,dpaux = <&dpaux0>;
2226 nvidia,dpaux = <&dpaux1>;
H A Dtegra210-p3450-0000.dts66 dpaux@54040000 {
87 nvidia,dpaux = <&dpaux>;
103 dpaux@545c0000 {
H A Dtegra186-p2771-0000.dts2449 dpaux@15040000 {
2468 nvidia,dpaux = <&dpaux>;
2483 dpaux@155c0000 {
H A Dtegra194-p3509-0000.dtsi2188 dpaux@155c0000 {
2192 dpaux@155d0000 {
2203 nvidia,dpaux = <&dpaux0>;
H A Dtegra210-p2597.dtsi16 dpaux@54040000 {
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-nyan-big-fhd.dts9 dpaux@545c0000 {
H A Dtegra124.dtsi291 dpaux: dpaux@545c0000 { label
292 compatible = "nvidia,tegra124-dpaux";
297 clock-names = "dpaux", "parent";
299 reset-names = "dpaux";
H A Dtegra124-venice2.dts44 nvidia,dpaux = <&dpaux>;
48 dpaux@545c0000 {
H A Dtegra124-nyan-blaze.dts19 dpaux@545c0000 {
H A Dtegra124-nyan-big.dts17 dpaux@545c0000 {
/linux/drivers/gpu/drm/tegra/
H A DMakefile22 dpaux.o \
H A Ddrm.h173 /* from dpaux.c */
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650-qrd.dts1282 * DPAUX -> WCD9395 -> USB_SBU -> USB-C
H A Dsm8650-hdk.dts1299 * DPAUX -> WCD9395 -> USB_SBU -> USB-C
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c5945 cmd.dp_aux_access.aux_control.dpaux.address = payload->address; in dc_process_dmub_aux_transfer_async()
5946 cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; in dc_process_dmub_aux_transfer_async()
5947 cmd.dp_aux_access.aux_control.dpaux.length = payload->length; in dc_process_dmub_aux_transfer_async()
5969 cmd.dp_aux_access.aux_control.dpaux.action = action; in dc_process_dmub_aux_transfer_async()
5972 memcpy(cmd.dp_aux_access.aux_control.dpaux.data, in dc_process_dmub_aux_transfer_async()
/linux/drivers/clk/tegra/
H A Dclk-tegra210.c2623 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
3105 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()

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