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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
19 * msm_dp_bridge_detect - callback to determine if connector is connected
20 * @bridge: Pointer to drm bridge structure
21 * Returns: Bridge's 'is connected' status
24 msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) in msm_dp_bridge_detect() argument
26 struct msm_dp *dp; in msm_dp_bridge_detect() local
28 dp = to_dp_bridge(bridge)->msm_dp_display; in msm_dp_bridge_detect()
30 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in msm_dp_bridge_detect()
31 str_true_false(dp->link_ready)); in msm_dp_bridge_detect()
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H A Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
33 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
190 { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
191 { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
192 { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
193 { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 },
194 { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x },
195 { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
196 { .compatible = "qcom,sc8280xp-dp", .data = &msm_dp_desc_sc8280xp },
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/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
16 #include <sound/hdmi-codec.h>
27 #include "cdn-dp-core.h"
28 #include "cdn-dp-reg.h"
30 static inline struct cdn_dp_device *bridge_to_dp(struct drm_bridge *bridge) in bridge_to_dp() argument
32 return container_of(bridge, struct cdn_dp_device, bridge); in bridge_to_dp()
63 { .compatible = "rockchip,rk3399-cdn-dp",
70 static int cdn_dp_grf_write(struct cdn_dp_device *dp, in cdn_dp_grf_write() argument
75 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_dp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Samsung SoC DP (Display Port) interface driver.
21 #include <drm/bridge/analogix_dp.h>
51 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_crtc_clock_enable() local
52 struct drm_encoder *encoder = &dp->encoder; in exynos_dp_crtc_clock_enable()
54 if (!encoder->crtc) in exynos_dp_crtc_clock_enable()
55 return -EPERM; in exynos_dp_crtc_clock_enable()
57 exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable); in exynos_dp_crtc_clock_enable()
75 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_get_modes() local
78 if (dp->plat_data.panel) in exynos_dp_get_modes()
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/linux/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/media-bus-format.h>
42 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
49 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
249 * struct zynqmp_dp_link_config - Common link config between source and sink
259 * struct zynqmp_dp_mode - Configured mode of DisplayPort
273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
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H A Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
47 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
58 * @bridge: The DP encoder bridge
61 * @dp: The DisplayPort controller
63 * @audio: DP audio data
78 struct drm_bridge *bridge; member
82 struct zynqmp_dp *dp; member
/linux/drivers/gpu/drm/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
4 * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
10 * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
11 * display bridge of the GE B850v3. There are two physical bridges on the video
12 * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). The
19 * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
61 struct drm_bridge bridge; member
71 struct i2c_adapter *adapter = client->adapter; in stdp2690_read_block()
76 .addr = client->addr, in stdp2690_read_block()
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H A Dtc358767.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver
6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP .
27 #include <linux/media-bus-format.h>
44 /* DSI D-PHY Layer registers */
77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
290 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
299 #define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */
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/linux/net/dsa/
H A Dtag.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 return ops->needed_headroom + ops->needed_tailroom; in dsa_tag_protocol_overhead()
35 struct dsa_port *cpu_dp = dev->dsa_ptr; in dsa_conduit_find_user()
36 struct dsa_switch_tree *dst = cpu_dp->dst; in dsa_conduit_find_user()
37 struct dsa_port *dp; in dsa_conduit_find_user() local
39 list_for_each_entry(dp, &dst->ports, list) in dsa_conduit_find_user()
40 if (dp->ds->index == device && dp->index == port && in dsa_conduit_find_user()
41 dp->type == DSA_PORT_TYPE_USER) in dsa_conduit_find_user()
42 return dp->user; in dsa_conduit_find_user()
48 * dsa_software_untag_vlan_aware_bridge: Software untagging for VLAN-aware bridge
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H A Dtag_8021q.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Binary structure of the fake 12-bit VID field (when the TPID is
19 * +-----------+-----+-----------------+-----------+-----------------------+
21 * +-----------+-----+-----------------+-----------+-----------------------+
23 * RSV - VID[11:10]:
26 * SWITCH_ID - VID[8:6]:
29 * VBID - { VID[9], VID[5:4] }:
30 * Virtual bridge ID. If between 1 and 7, packet targets the broadcast
31 * domain of a bridge. If transmitted as zero, packet targets a single
34 * PORT - VID[3:0]:
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H A Duser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * net/dsa/user.c - user device handling
4 * Copyright (c) 2008-2009 Marvell Semiconductor
70 return ds->ops->port_fdb_add && ds->ops->port_fdb_del && in dsa_switch_supports_uc_filtering()
71 ds->fdb_isolation && !ds->vlan_filtering_is_global && in dsa_switch_supports_uc_filtering()
72 !ds->needs_standalone_vlan_filtering; in dsa_switch_supports_uc_filtering()
77 return ds->ops->port_mdb_add && ds->ops->port_mdb_del && in dsa_switch_supports_mc_filtering()
78 ds->fdb_isolation && !ds->vlan_filtering_is_global && in dsa_switch_supports_mc_filtering()
79 !ds->needs_standalone_vlan_filtering; in dsa_switch_supports_mc_filtering()
86 const unsigned char *addr = standalone_work->addr; in dsa_user_standalone_event_work()
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H A Dtrace.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright 2022-2023 NXP
10 switch (db->type) { in dsa_db_print()
12 sprintf(buf, "port %s", db->dp->name); in dsa_db_print()
15 sprintf(buf, "lag %s id %d", db->lag.dev->name, db->lag.id); in dsa_db_print()
18 sprintf(buf, "bridge %s num %d", db->bridge.dev->name, in dsa_db_print()
19 db->bridge.num); in dsa_db_print()
27 const char *dsa_port_kind(const struct dsa_port *dp) in dsa_port_kind() argument
29 switch (dp->type) { in dsa_port_kind()
H A Ddsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2008-2009 Marvell Semiconductor
53 * dsa_lag_map() - Map LAG structure to a linear LAG array
59 * driver by setting ds->num_lag_ids. It is perfectly legal to leave
61 * no-ops.
67 for (id = 1; id <= dst->lags_len; id++) { in dsa_lag_map()
69 dst->lags[id - 1] = lag; in dsa_lag_map()
70 lag->id = id; in dsa_lag_map()
78 * driver can then return -EOPNOTSUPP back to DSA, which will in dsa_lag_map()
84 * dsa_lag_unmap() - Remove a LAG ID mapping
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H A Dtag_sja1105.c1 // SPDX-License-Identifier: GPL-2.0
23 /* Trap-to-host format (no trailer present) */
33 /* Meta frame format (for 2-step TX timestamps) */
74 return ds->tagger_data; in sja1105_tagger_private()
77 /* Similar to is_link_local_ether_addr(hdr->h_dest) but also covers PTP */
81 u64 dmac = ether_addr_to_u64(hdr->h_dest); in sja1105_is_link_local()
83 if (ntohs(hdr->h_prot in sja1105_is_link_local()
140 sja1105_defer_xmit(struct dsa_port * dp,struct sk_buff * skb) sja1105_defer_xmit() argument
174 sja1105_xmit_tpid(struct dsa_port * dp) sja1105_xmit_tpid() argument
213 struct dsa_port *dp = dsa_user_to_port(netdev); sja1105_imprecise_xmit() local
240 sja1105_pvid_tag_control_pkt(struct dsa_port * dp,struct sk_buff * skb,u8 pcp) sja1105_pvid_tag_control_pkt() argument
269 struct dsa_port *dp = dsa_user_to_port(netdev); sja1105_xmit() local
297 struct dsa_port *dp = dsa_user_to_port(netdev); sja1110_xmit() local
386 struct dsa_port *dp = dsa_user_to_port(skb->dev); sja1105_rcv_meta_state_machine() local
420 struct dsa_port *dp = dsa_user_to_port(skb->dev); sja1105_rcv_meta_state_machine() local
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
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H A Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
13 The TC358767/TC358867/TC9595 is bridge device which
14 converts DSI/DPI to eDP/DP .
19 - items:
20 - enum:
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H A Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analogix Display Port bridge
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
26 const: dp
28 force-hpd:
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display Port) core interface driver.
22 #include <drm/bridge/analogix_dp.h>
40 static void analogix_dp_init_dp(struct analogix_dp_device *dp) in analogix_dp_init_dp() argument
42 analogix_dp_reset(dp); in analogix_dp_init_dp()
44 analogix_dp_swreset(dp); in analogix_dp_init_dp()
46 analogix_dp_init_analog_param(dp); in analogix_dp_init_dp()
47 analogix_dp_init_interrupt(dp); in analogix_dp_init_dp()
50 analogix_dp_enable_sw_function(dp); in analogix_dp_init_dp()
52 analogix_dp_config_interrupt(dp); in analogix_dp_init_dp()
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/linux/include/net/
H A Ddsa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/net/dsa.h - Driver for Distributed Switch Architecture switch chips
4 * Copyright (c) 2008-2009 Marvell Semiconductor
127 /* Notifier chain for switch-wide events */
136 /* Maps offloaded LAG netdevs to a zero-based linear ID for
168 /* LAG IDs are one-based, the dst->lags array is zero-based */
170 for ((_id) = 1; (_id) <= (_dst)->lags_len; (_id)++) \
171 if ((_dst)->lags[(_id) - 1])
174 list_for_each_entry((_dp), &(_dst)->ports, list) \
178 list_for_each_entry((_dp), &(_ds)->dst->ports, list) \
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/linux/tools/testing/selftests/net/
H A Dtest_vxlan_mdb.sh2 # SPDX-License-Identifier: GPL-2.0
12 # +------------------------------------+ +------------------------------------+
19 # | +---------+---------+ | | +---------+---------+ |
33 # +-----------------|------------------+ +-----------------|------------------+
35 # +-----------------|------------------+ +-----------------|------------------+
49 # | +---------+---------+ | | +---------+---------+ |
56 # +------------------------------------+ +------------------------------------+
122 # All tests in this script. Can be overridden with -t option.
140 if [ ${rc} -eq ${expected} ]; then
141 printf "TEST: %-60s [ OK ]\n" "${msg}"
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence MHDP8546 DP bridge driver.
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
[all …]
/linux/drivers/usb/typec/ucsi/
H A Ducsi_yoga_c630.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2022-2024, Linaro Ltd
18 #include <linux/platform_data/lenovo-yoga-c630.h>
21 #include <drm/bridge/aux-bridge.h>
36 struct auxiliary_device *bridge; member
45 *version = uec->version; in yoga_c630_ucsi_read_version()
56 ret = yoga_c630_ec_ucsi_read(uec->ec, buf); in yoga_c630_ucsi_read_cci()
72 ret = yoga_c630_ec_ucsi_read(uec->ec, buf); in yoga_c630_ucsi_read_message_in()
86 return yoga_c630_ec_ucsi_write(uec->ec, (u8*)&command); in yoga_c630_ucsi_async_control()
97 * EC doesn't return connector's DP mode even though it is supported. in yoga_c630_ucsi_sync_control()
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/linux/drivers/net/dsa/
H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
49 if (priv->bus) in mt7530_mutex_lock()
50 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
56 if (priv->bus) in mt7530_mutex_unlock()
57 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
63 struct mii_bus *bus = priv->bus; in core_write()
69 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
75 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
81 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
87 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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H A Drzn1_a5psw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2022 Schneider-Electric
73 writel(value, a5psw->base + offset); in a5psw_reg_writel()
78 return readl(a5psw->base + offset); in a5psw_reg_readl()
85 spin_lock(&a5psw->reg_lock); in a5psw_reg_rmw()
92 spin_unlock(&a5psw->reg_lock); in a5psw_reg_rmw()
156 ret = readl_poll_timeout(a5psw->base + A5PSW_LK_ADDR_CTRL, *ctrl, in a5psw_lk_execute_ctrl()
160 dev_err(a5psw->dev, "LK_CTRL timeout waiting for BUSY bit\n"); in a5psw_lk_execute_ctrl()
169 mutex_lock(&a5psw->lk_lock); in a5psw_port_fdb_flush()
171 mutex_unlock(&a5psw->lk_lock); in a5psw_port_fdb_flush()
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
114 struct drm_bridge bridge; member
135 /* protect the plugged_cb as it's used in both bridge ops and audio */
402 .name = "mtk-dp-registers",
407 return container_of(b, struct mtk_dp, bridge); in mtk_dp_from_bridge()
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