| /titanic_53/usr/src/uts/common/os/ |
| H A D | cpu_pm.c | 44 * Idle Power Management domains can enter power savings states when they are
46 * for performance (in the form of latency to transition from the idle state
49 * For each active and idle power domain the CMT subsystem instantiates, a
54 * utilization of the power domain. The power manager recieves the events,
56 * the domain's power/performance state be changed.
59 * manager will request the CPUs in the domain run at their fastest (and most
60 * power consuming) state. When the domain becomes idle (utilization at zero),
71 * Avoiding state thrashing in the presence of transient periods of utilization
72 * and idleness while still being responsive to non-transient periods is key.
74 * state transitions when a significant amount of transient idle or transient
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| /titanic_53/usr/src/uts/i86pc/os/cpupm/ |
| H A D | cpupm_mach.c | 64 * Since all CPUs in a domain should have identical properties, this
66 * that will redefine the topspeed for all devices in a CPU domain.
98 * c-state tunables
101 * recalculating c-state statistics. When a CPU goes idle it checks
103 * caculated which C-state to go to.
105 * cpupm_cs_idle_cost_tunable is the ratio of time CPU spends executing + idle
106 * divided by time spent in the idle state transitions.
108 * in idle latency. The worst case performance will be 90% of non Deep C-state
111 * cpupm_cs_idle_save_tunable is how long we must stay in a deeper C-state
116 uint32_t cpupm_cs_idle_save_tunable = 2; /* idle power savings */
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| H A D | cpu_idle.c | 26 * Copyright (c) 2009-2010, Intel Corporation.
66 * the flag of always-running local APIC timer.
73 * Interfaces for modules implementing Intel's deep c-state.
76 "Generic ACPI C-state Support",
97 * kstat update function of the c-state info
102 cpu_acpi_cstate_t *cstate = ksp->ks_private; in cpu_idle_kstat_update()
108 if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { in cpu_idle_kstat_update()
111 } else if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_SYSTEM_IO) { in cpu_idle_kstat_update()
119 cpu_idle_kstat.cs_latency.value.ui32 = cstate->cs_latency; in cpu_idle_kstat_update()
120 cpu_idle_kstat.cs_power.value.ui32 = cstate->cs_power; in cpu_idle_kstat_update()
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| /titanic_53/usr/src/uts/common/sys/ |
| H A D | cpu_pm.h | 50 * Power Managable CPU Domain Types
53 CPUPM_DTYPE_ACTIVE, /* Active Power Domain */
54 CPUPM_DTYPE_IDLE /* Idle Power Domain */
58 * CPUPM state names for policy implementation.
68 * Possible states for the domain's transience governor
88 * CPU Power Domain State
96 * CPU Power Domain
99 id_t cpd_id; /* Domain ID */
100 cpupm_dtype_t cpd_type; /* Active or Idle */
102 cpupm_state_t *cpd_state; /* Current State */
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| /titanic_53/usr/src/uts/sun4v/os/ |
| H A D | mach_startup.c | 58 * CPU IDLE optimization variables/routines
65 * The probe fires when the CPU undergoes an idle state change (e.g. hv yield)
66 * The agument passed is the state to which the CPU is transitioning.
87 mmu_fault_status_area + (MMFSA_SIZE * CPU->cpu_id); in setup_trap_table()
109 processorid_t cpu_sid = cpup->cpu_seqid; in cpu_halt()
110 cpupart_t *cp = cpup->cpu_part; in cpu_halt()
112 volatile int *p = &cpup->cpu_disp->disp_nrunnable; in cpu_halt()
121 if (CPU->cpu_flags & CPU_OFFLINE) in cpu_halt()
140 cpup->cpu_disp_flags |= CPU_DISP_HALTED; in cpu_halt()
142 bitset_atomic_add(&cp->cp_haltset, cpu_sid); in cpu_halt()
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| /titanic_53/usr/src/uts/i86pc/sys/ |
| H A D | cpupm_mach.h | 81 * Data kept for each C-state power-domain.
84 uint32_t cs_next_cstate; /* computed best C-state */
87 uint32_t cs_type; /* current ACPI idle type */
89 hrtime_t cs_idle_enter; /* entered idle */
90 hrtime_t cs_idle_exit; /* left idle */
93 hrtime_t cs_idle; /* time idle */
95 hrtime_t cs_smpl_idle; /* idle time in last sample */
96 uint64_t cs_smpl_idle_pct; /* % idle time in last smpl */
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| /titanic_53/usr/src/cmd/idmap/idmapd/ |
| H A D | adutils.c | 75 * data used for validating search result entries for name->SID
79 char *edomain; /* expected domain name */
83 char **domain; /* name of domain of object */ member
124 * Idle connection reaping side of connection management
126 * Every minute wake up and look for connections that have been idle for
141 * nanosleep(3RT) is thead-safe (no SIGALRM) and more in adreaper()
157 int ret = -1; in idmap_add_ds()
195 idmap_query_state_t **state) in idmap_lookup_batch_start() argument
200 *state = NULL; in idmap_lookup_batch_start()
205 (nqueries - 1) * sizeof (idmap_q_t)); in idmap_lookup_batch_start()
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| /titanic_53/usr/src/lib/libsasl/include/ |
| H A D | saslplug.h | 6 /* saslplug.h -- API for SASL plug-ins */
31 * intermediate HMAC state
42 * conn -- the connection to lookup a callback for
43 * callbacknum -- the number of the callback
45 * pproc -- pointer to the callback function (set to NULL on failure)
46 * pcontext -- pointer to the callback context (set to NULL on failure)
48 * SASL_OK -- no error
49 * SASL_FAIL -- unable to find a callback of the requested type
50 * SASL_INTERACT -- caller must use interaction to get data
64 /* utility function set for plug-ins */
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| /titanic_53/usr/src/uts/i86xpv/os/ |
| H A D | mp_xen.c | 30 * VCPUs can be controlled in one of two ways; through the domain itself
38 * hypervisor on the idle thread). It must be up since a downed VCPU cannot
43 * if it has run previously, its software state (cpu_t, machcpu structures, IPI
50 * "online": the VCPU is running. Corresponds to a CPU state other than
54 * P_POWEROFF state, and only the domain can change between P_ONLINE, P_NOINTR,
56 * idempotently, as we'll get 'duplicate' entries when we resume a domain.
58 * Note that the xenstore configuration is strictly advisory, in that a domain
59 * can choose to ignore it and still power up a VCPU in the offline state. To
63 * Powering off a VCPU and suspending the domain use similar code. The
65 * state: it must have a saved PCB, and not be responding to interrupts
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| /titanic_53/usr/src/uts/sun4u/starcat/ml/ |
| H A D | drmach_asm.s | 161 ! default casx specifies ASI_PRIMARY, which if non-zero, can
202 ! Macro to check if a Panther MC is idle. The EMU Activity
205 ! to verify the MCU is indeed idle. A single non-idle status
206 ! will fail the idle check. This could be made more lenient
211 ! 0 is returned in this register if MCU is idle and
212 ! queues are empty. Otherwise, -1 is returned in this
246 ! is ready to be removed from domain coherency.
369 ! state I before removing this processor from the
413 ! [%o1] = 1 if failed to idle memory controller, otherwise unmodified.
417 ! the copy-rename process. drmach_rename is copied to a cpu's sram
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| /titanic_53/usr/src/uts/sun4/os/ |
| H A D | mp_startup.c | 60 /* bit mask of cpus ready for x-calls, protected by cpu_lock */
88 return (TRAP_TSIZE * (max_ncpus - 1)); in calc_traptrace_sz()
110 * Set state to TS_ONPROC since this thread will start running in common_startup_init()
117 tp->t_preempt = 1; in common_startup_init()
118 tp->t_bound_cpu = cp; in common_startup_init()
119 tp->t_affinitycnt = 1; in common_startup_init()
120 tp->t_cpu = cp; in common_startup_init()
121 tp->t_disp_queue = cp->cpu_disp; in common_startup_init()
124 CPUSET_ADD(sfmmup->sfmmu_cpusran, cpuid); in common_startup_init()
129 sp = tp->t_stk; in common_startup_init()
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| /titanic_53/usr/src/uts/common/xen/public/ |
| H A D | vcpu.h | 35 * @extra_args == Operation-specific extra arguments (NULL if none).
40 * newly-initialised VCPU will not run until it is brought up by VCPUOP_up.
43 * state for the VCPU.
54 * Bring down a VCPU (i.e., make it non-runnable).
58 * idea to ensure that the VCPU has entered a non-critical loop before
62 * references to domain memory. Even a VCPU that is down still holds
64 * practise to move a VCPU onto an 'idle' or default page table, LDT and
73 * Return information about the state and running time of a VCPU.
78 /* VCPU's current state (RUNSTATE_*). */
79 int state; member
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| H A D | platform.h | 4 * Hardware platform operations. Intended for use by domain-0 kernel.
24 * Copyright (c) 2002-2006, K Fraser
49 * Request memory range (@mfn, @mfn+@nr_mfns-1) to have type @type.
50 * On x86, @type is an architecture-defined MTRR memory type.
53 * (x86-specific).
69 * Tear down an existing memory-range type. If @handle is remembered then it
73 * (x86-specific).
84 /* Read current type of an MTRR (x86-specific). */
107 #define QUIRK_NOIRQBALANCING 1 /* Do not restrict IO-APIC RTE targets */
108 #define QUIRK_IOAPIC_BAD_REGSEL 2 /* IO-APIC REGSEL forgets its value */
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| /titanic_53/usr/src/lib/libadutils/common/ |
| H A D | adutils.c | 43 /* List of DSs, needed by the idle connection reaper thread */
48 * List of query state structs -- needed so we can "route" LDAP results
56 static void adutils_lookup_batch_unlock(adutils_query_state_t **state);
121 * bytes #2-#7: SID authority, big-endian 48-bit unsigned int in adutils_getsid()
123 * followed by RID count RIDs, each a little-endian, unsigned in adutils_getsid()
124 * 32-bit int. in adutils_getsid()
130 if (bval->bv_len > 8 && bval->bv_val[0] == 0x01 && in adutils_getsid()
131 bval->bv_len == 1 + 1 + 6 + bval->bv_val[1] * 4) { in adutils_getsid()
132 v = (uchar_t *)bval->bv_val; in adutils_getsid()
133 sidp->version = v[0]; in adutils_getsid()
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| /titanic_53/usr/src/man/man1m/ |
| H A D | pppd.1m | 8 pppd \- point to point protocol daemon
18 The point-to-point protocol (PPP) provides a method for transmitting datagrams
19 over serial point-to-point links. PPP is composed of three components: a
22 establishing and configuring different network-layer protocols.
39 options on the command line. (Command-line options are scanned for the terminal
49 double-quotes ("). A backslash (\e) quotes the succeeding character. A hash (#)
64 source cannot be overridden by a non-privileged user.
74 the baud rate unchanged. This option is normally needed for dial-out only.
85 \fBpppd\fR asks the peer to send these characters as a 2-byte escape sequence.
92 \fBdefault-asyncmap\fR option to disable negotiation and escape all control
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| /titanic_53/usr/src/man/man3socket/ |
| H A D | socket.3socket | 10 socket \- create an endpoint for communication
14 \fBcc\fR [ \fIflag\fR ... ] \fIfile\fR ... \fB-lsocket\fR \fB -lnsl \fR [ \fIlibrary\fR ... ]
18 \fBint\fR \fBsocket\fR(\fBint\fR \fIdomain\fR, \fBint\fR \fItype\fR, \fBint\fR \fIprotocol\fR);
28 The \fIdomain\fR argument specifies the protocol family within which
88 The \fItype\fR may be augmented by a bitwise-inclusive-OR of flags from the
127 protocol family and type required. If a non-zero protocol has been specified
133 A \fBSOCK_STREAM\fR type provides sequenced, reliable, two-way connection-based
134 byte streams. An out-of-band data transmission mechanism may be supported. A
137 provide a sequenced, reliable, two-way connection-based data transmission path
147 The \fIprotocol\fR parameter is a protocol-family-specific value which
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| /titanic_53/usr/src/uts/common/xen/dtrace/ |
| H A D | xdt.c | 30 * NOTE: This provider is PRIVATE. It is intended as a short-term solution and
31 * may disappear or be re-implemented at anytime.
33 * This provider isn't suitable as a general-purpose solution for a number of
41 * --------------
45 * probes record events in contiguous per-CPU trace buffers.
47 * +---------+
48 * +------+ | |
49 * | CPUn |----> | BUFFERn |
50 * +------+ | |
51 * +---------+- tbuf.va + (tbuf.size * n)
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| /titanic_53/usr/src/uts/sun4u/serengeti/io/ |
| H A D | sbdp_cpu.c | 33 * connect,unconfigured: Idling in OBP's idle loop
36 * State transitions:
39 * ------------> ------------>
42 * <----------- <-------------
49 * ------------> ------------------------->
52 * <----------- <-------------------------
59 * it is an SIR, and re-enters OBP as a slave. When the operation
125 rv = -1; in sbdp_disconnect_cpu()
134 bdp = &wnodep->bds[bd]; in sbdp_disconnect_cpu()
136 mutex_enter(&bdp->bd_mutex); in sbdp_disconnect_cpu()
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| /titanic_53/usr/src/uts/sun4u/starfire/io/ |
| H A D | idn_proto.c | 28 * Inter-Domain Network
30 * IDN Protocol functions to support domain link/unlink/reconfig.
263 * - receive message.
264 * - call check-function for current state.
265 * - if (check-function == ok) then
266 * call action-function for current state.
268 * call error-function for current state.
269 * - transition state based on check results.
270 * - if (next state == final state) then
271 * call final-function.
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| /titanic_53/usr/src/uts/i86pc/os/ |
| H A D | machdep.c | 150 * Occassionally the kernel knows better whether to power-off or reboot.
155 * The panicbuf array is used to record messages and state:
170 * maxphys - used during physio
171 * klustsize - used for klustering by swapfs and specfs
173 int maxphys = 56 * 1024; /* XXX See vm_subr.c - max b_count in physio */
193 * "mdep" is interpreted as a character pointer; if non-null, it is a pointer
231 * XXX - rconsvp is set to NULL to ensure that output messages in mdboot()
298 (panic_lbolt - lbolt_at_boot) > fastreboot_onpanic_uptime) { in mdboot()
315 if (reset_status == -1) { in mdboot()
373 /* mdpreboot - may be called prior to mdboot while root fs still mounted */
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| /titanic_53/usr/src/uts/sun4u/starfire/sys/ |
| H A D | idn.h | 25 * Inter-Domain Network
64 * IDN_PROP_SMRSIZE - User specified size in MBytes.
65 * IDN_PROP_SMRADDR - OBP's internal physical address of the region.
69 #define IDN_PROP_SMRSIZE "idn-smr-size"
70 #define IDN_PROP_SMRADDR "idn-smr-addr"
75 * Number of seconds between AWOL messages on a per-domain basis.
110 * Master domain to the Slaves for the purpose of communicating
123 * Portion of IDN_SMR_BUFSIZE that can contain raw non-IDN dependent
127 * (IDN_SMR_BUFSIZE - sizeof (smr_pkthdr_t) - IDN_ALIGNSIZE)
133 * Req: IDN_MTU <= IDN_DATA_SIZE - sizeof (ether_header)
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| /titanic_53/usr/src/uts/common/io/hxge/ |
| H A D | hxge_peu_hw.h | 232 * Master Data Parity Error - set if all the following conditions
236 * Fast Back-to-Back Capable (N/A in PCIE)
238 * Capabilities List - presence of extended capability item.
241 * Fast Back-to-Back Enable (N/A in PCIE)
246 * The device can issue Memory Write-and-Invalidate commands (N/A
348 * Multi-Function Device: dbi writeable
376 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0
434 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX
491 * Description: Virtualization BAR0 - Previously for Hydra
568 * Subsystem ID as assigned by PCI-SIG : dbi writeable
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| /titanic_53/usr/src/cmd/cmd-inet/usr.lib/mdnsd/ |
| H A D | PosixDaemon.c | 1 /* -*- Mode: C; tab-width: 4 -*-
3 * Copyright (c) 2003-2004 Apple Computer, Inc. All rights reserved.
9 * http://www.apache.org/licenses/LICENSE-2.0
25 // error, which prevents compilation because we build with "-Werror".
26 // Since this is supposed to be portable cross-platform code, we don't care that daemon is
57 static domainname DynDNSZone; // Default wide-area zone for service registration
69 // On successful registration of dot-local mDNS host name, daemon may want to check if in mDNS_StatusCallback()
72 // On Mac OS X we store the current dot-local mDNS host name in the SCPreferences store, in mDNS_StatusCallback()
88 // -- all client layers running on top of mDNSPosix.c need to handle network configuration changes,
89 // not only the Unix Domain Socket Daemon
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| /titanic_53/usr/src/uts/sun4u/starcat/io/ |
| H A D | axq.c | 118 * If non-zero, iopause will be asserted during DDI_SUSPEND.
145 * AXQ event-names and event masks. The number
310 if (softsp->slotnum && softsp->paused && use_axq_iopause && in axq_attach()
312 *softsp->axq_domain_ctrl &= ~AXQ_DOMCTRL_PAUSE; in axq_attach()
313 softsp->paused = 0; in axq_attach()
326 /* Set the dip in the soft state */ in axq_attach()
327 softsp->dip = devi; in axq_attach()
330 if ((softsp->portid = (int)ddi_getprop(DDI_DEV_T_ANY, softsp->dip, in axq_attach()
331 DDI_PROP_DONTPASS, "portid", -1)) == -1) { in axq_attach()
337 softsp->expid = softsp->portid >> 5; in axq_attach()
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| /titanic_53/usr/src/uts/sun4u/excalibur/io/ |
| H A D | xcalppm.c | 27 * Platform Power Management driver for SUNW,Sun-Blade-1000
49 * xcppm_dev structures the domain_lock for the affected domain must be held.
64 * the domain lock, then walking the list of affected devices and acquiring
66 * each of the power locks is freed, followed by freeing the domain lock.
70 * acquiring the domain lock and directly calling the framework routine for
87 * domains is changed to LOCK_ONE to simplify other code. The domain
114 * one-to-one correspondence with the cpu_level array.
188 &mod_driverops, /* type of module - pseudo */
240 &unitp->hndls.bbc_estar_ctrl); in xcppm_map_all_regs()
242 unitp->regs.bbc_estar_ctrl = (uint16_t *)(base_addr + in xcppm_map_all_regs()
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