Home
last modified time | relevance | path

Searched +full:disable +full:- +full:mmu +full:- +full:reset (Results 1 – 25 of 171) sorted by relevance

1234567

/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
32 select GENERIC_STRNCPY_FROM_USER if MMU
33 select GENERIC_STRNLEN_USER if MMU
70 config MMU config
90 source "arch/arc/plat-tb10x/Kconfig"
91 source "arch/arc/plat-axs10x/Kconfig"
92 source "arch/arc/plat-hsdk/Kconfig"
110 ISA for the Next Generation ARC-HS cores
128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
[all …]
/linux/drivers/iommu/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "ARM Ltd. System MMU (SMMU) Support"
11 Support for implementations of the ARM System MMU architecture
19 bool "Support the legacy \"mmu-masters\" devicetree bindings"
22 Support for the badly designed and deprecated "mmu-masters"
31 bool "Disable unmatched stream bypass by default" if EXPERT
36 securely, and you don't want to boot with the 'arm-smmu.disable_bypass=0'
40 Note that 'arm-smmu.disable_bypass=1' will still take precedence.
43 bool "Enable errata workaround for CPRE in SMMU reset path"
46 Say Y here (by default) to apply workaround to disable
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
69 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
72 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
73 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
79 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
80 #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
[all …]
/linux/arch/arm64/kernel/
H A Dhyp-stub.S1 /* SPDX-License-Identifier: GPL-2.0-only */
35 ventry elx_sync // Synchronous 64-bit EL1
36 ventry el1_irq_invalid // IRQ 64-bit EL1
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
38 ventry el1_error_invalid // Error 64-bit EL1
40 ventry el1_sync_invalid // Synchronous 32-bit EL1
41 ventry el1_irq_invalid // IRQ 32-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
43 ventry el1_error_invalid // Error 32-bit EL1
66 beq 9f // Nothing to reset!
[all …]
/linux/sound/pci/aw2/
H A Daw2-saa7146.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Jean-Christian Hassler <jhassler@free.fr>
24 #include "aw2-saa7146.h"
26 #include "aw2-tsl.c"
28 #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
29 #define READREG(addr) readl(chip->base_addr + (addr))
38 /* chip-specific destructor */
41 /* disable all irqs */ in snd_aw2_saa7146_free()
44 /* reset saa7146 */ in snd_aw2_saa7146_free()
48 chip->base_addr = NULL; in snd_aw2_saa7146_free()
[all …]
/linux/arch/arm/mm/
H A Dproc-sa110.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa110.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-110.
18 #include <asm/asm-offsets.h>
21 #include <asm/pgtable-hwdef.h>
24 #include "proc-macros.S"
47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
[all …]
H A Dproc-sa1100.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa1100.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * MMU functions for SA110
11 * functions on the StrongARM-1100 and StrongARM-1110.
15 * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
23 #include <asm/asm-offsets.h>
26 #include <asm/pgtable-hwdef.h>
28 #include "proc-macros.S"
[all …]
H A Dproc-v6.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v6.S
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 * Perform a soft reset of the system. Put the CPU into the
54 * same state as it would be if it had been reset, and branch
55 * to what would be the reset vector.
57 * - loc - location to jump to for soft reset
[all …]
H A Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
15 #include <asm/asm-offsets.h>
17 #include <asm/pgtable-hwdef.h>
20 #include "proc-macros.S"
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 .arch armv7-a
38 mcr p15, 0, r0, c1, c0, 0 @ disable caches
[all …]
/linux/Documentation/virt/kvm/arm/
H A Dhyp-abi.rst1 .. SPDX-License-Identifier: GPL-2.0
11 hypervisor), or any hypervisor-specific interaction when the kernel is
20 mode, but still needs to interact with it, allowing a built-in
28 Unless specified otherwise, any built-in hypervisor must implement
45 Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials
57 Mask all exceptions, disable the MMU, clear I+D bits, move the arguments
65 Finish configuring EL2 depending on the command-line options,
68 supporting VHE, the EL2 MMU being off, and VHE not being disabled by
71 Any other value of r0/x0 triggers a hypervisor-specific handling,
76 clobber any of the caller-saved registers (x0-x18 on arm64, r0-r3 and
/linux/arch/arm/mach-tegra/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
29 #include <asm/proc-fns.h>
36 #include "reset.h"
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
143 return -EBUSY; in tegra_sleep_cpu()
148 * MMU-on if cache maintenance is done via Trusted Foundations in tegra_sleep_cpu()
150 * if any of secondary CPU's is online and this is the LP2-idle in tegra_sleep_cpu()
151 * code-path only for Tegra20/30. in tegra_sleep_cpu()
154 if (trusted_foundations_registered() && outer_cache.disable) in tegra_sleep_cpu()
[all …]
H A Dsleep-tegra20.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
50 .arch armv7-a
89 * puts the current cpu in reset
102 * r0 is cpu to reset
104 * puts the specified CPU in wait-for-event mode on the flow controller
105 * and puts the CPU in reset
110 * corrupts r0-r3, r12
[all …]
/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-habanalabs46 the generic Linux user-space PCI mapping) because the DDR bar
61 the generic Linux user-space PCI mapping) because the DDR bar
77 Linux user-space PCI mapping) because the amount of internal
91 Valid values are "disable", "enable", "suspend", "resume".
99 certain error cases, after which the device is reset.
212 What: /sys/kernel/debug/accel/<parent_device>/mmu
220 echo "1 0x1000" > /sys/kernel/debug/accel/<parent_device>/mmu
226 Description: Check and display page fault or access violation mmu errors for
228 e.g. to display error info for MMU hw cap bit 9, you need to do:
241 Linux user-space PCI mapping) because this space is protected
[all …]
/linux/drivers/accel/habanalabs/common/mmu/
H A Dmmu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
16 * hl_mmu_get_funcs() - get MMU functions structure
21 * @return appropriate MMU functions structure
26 return &hdev->mmu_func[pgt_residency]; in hl_mmu_get_funcs()
31 struct asic_fixed_properties *prop = &hdev->asic_prop; in hl_is_dram_va()
33 return hl_mem_area_inside_range(virt_addr, prop->dmmu.page_size, in hl_is_dram_va()
34 prop->dmmu.start_addr, in hl_is_dram_va()
35 prop->dmmu.end_addr); in hl_is_dram_va()
39 * hl_mmu_init() - initialize the MMU module.
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 depends on MMU
58 OMAP Video Encoder support for S-Video and composite TV-out.
93 SDI is a high speed one-way display serial bus between the host
103 DSI is a high speed half-duplex serial interface between the host
127 bool "Sleep 20ms after VENC reset"
130 There is a 20ms sleep after VENC reset which seemed to fix the
131 reset. The reason for the bug is unclear, and it's also unclear
135 disable the sleep if it doesn't cause problems on your platform.
/linux/drivers/iommu/
H A Dipmmu-vmsa.c1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
71 struct ipmmu_vmsa_device *mmu; member
93 /* -----------------------------------------------------------------------------
[all …]
/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
13 #include "../include/hw_ip/mmu/mmu_general.h"
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
95 /* Default value for device reset trigger , an invalid value */
[all …]
/linux/arch/m68k/mac/
H A Dmisc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Miscellaneous Mac68K-specific stuff
31 * Offset between Unix time (1970-based) and Mac time (1904-based). Cuda and PMU
33 * need to be changed to interpret wrapped times as post-2040.
157 * Inside Mac has no information about two-byte RTC commands but
168 * data should point to a one-byte buffer for the
190 if (command & 0xFF00) { /* extended (two-byte) command */ in via_rtc_command()
194 } else { /* one-byte command */ in via_rtc_command()
204 /* All done, disable the RTC */ in via_rtc_command()
239 * This only works on machines with the VIA-based PRAM/RTC, which
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_setup_6xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include <asm/asm-offsets.h>
15 #include <asm/mmu.h>
16 #include <asm/feature-fixups.h>
100 bne 1f /* don't invalidate the D-cache */
194 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
208 * Looks like we have to disable NAP feature for some PLL settings...
239 * just ensure we don't disable it.
245 * the firmware. If any, we disable NAP capability as
274 xoris r11,r11,HID0_DPM@h /* disable dynamic power mgmt */
[all …]
H A Dhead_8xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Low-level exception handlers and MMU support
13 * This file contains low-level support and setup for PowerPC 8xx
25 #include <asm/mmu.h>
30 #include <asm/asm-offsets.h>
32 #include <asm/code-patching-asm.h>
52 * support an ELF compressed (zImage) boot from EPPC-Bug because the
56 * r5: initrd_end - unused if r4 is 0
66 * We first initialize the MMU to support 8M byte pages, then load one
[all …]
/linux/arch/arm/mach-exynos/
H A Dmcpm-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 // Based on arch/arm/mach-vexpress/dcscb.c
7 #include <linux/arm-cci.h>
12 #include <linux/soc/samsung/exynos-regs-pmu.h>
44 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
65 return -EINVAL; in exynos_cpu_powerup()
74 * they should be reset during power up cpu. in exynos_cpu_powerup()
81 * Before we reset the Little cores, we should wait in exynos_cpu_powerup()
87 timeout--; in exynos_cpu_powerup()
95 return -ETIMEDOUT; in exynos_cpu_powerup()
[all …]
/linux/drivers/gpu/drm/v3d/
H A Dv3d_irq.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
43 struct drm_device *dev = &v3d->drm; in v3d_overflow_mem_work()
52 obj = &bo->base.base; in v3d_overflow_mem_work()
63 spin_lock_irqsave(&v3d->job_lock, irqflags); in v3d_overflow_mem_work()
64 if (!v3d->bin_job) { in v3d_overflow_mem_work()
65 spin_unlock_irqrestore(&v3d->job_lock, irqflags); in v3d_overflow_mem_work()
70 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); in v3d_overflow_mem_work()
71 spin_unlock_irqrestore(&v3d->job_lock, irqflags); in v3d_overflow_mem_work()
75 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT); in v3d_overflow_mem_work()
[all …]
/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_issues.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */
16 /* Need way to guarantee that all previously-translated memory accesses
20 /* On job complete with non-done the cache is not flushed */
43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
47 /* Disable the Pause Buffer in the LS pipe. */
53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
57 /* HT: Tiler returns TERMINATED for non-terminated command */
61 * address before the MMU page table has been read by the GPU */
68 /* MMU TLB invalidation hazards */
[all …]
/linux/arch/x86/kvm/mmu/
H A Dspte.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
13 #include "mmu.h"
71 * KVM can actually enable MMIO caching depends on vendor-specific in kvm_mmu_spte_module_init()
94 u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; in make_mmio_spte()
99 spte |= vcpu->kvm->arch.shadow_mmio_value | access; in make_mmio_spte()
119 * and only treat UC/UC-/WC pages as MMIO. in __kvm_is_mmio_pfn()
124 pfn_to_hpa(pfn + 1) - 1, in __kvm_is_mmio_pfn()
143 struct kvm_mmu_page *root = root_to_sp(vcpu->arch.mmu->root.hpa); in kvm_track_host_mmio_mapping()
146 WRITE_ONCE(root->has_mapped_host_mmio, true); in kvm_track_host_mmio_mapping()
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Etnaviv Project
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
16 #include <linux/reset.h>
32 { .name = "etnaviv-gpu,2d" },
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
[all …]

1234567