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Searched full:dcfclk (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.h40 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
43 // fudge factor for min dcfclk calclation
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
43 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
42 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Dsmu13_driver_if_v13_0_4.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Dsmu15_driver_if_v15_0_0.h46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/
H A Ddcn60_clk_mgr.c527 /* DCFCLK */ in dcn60_populate_clk_table()
726 // read dcfclk in dcn60_dump_clk_registers_internal()
760 regs_and_bypass->dcfclk = count_to_khz(internal.CLK8_CLK0_CURRENT_CNT, timer_ths, refclk_khz); in dcn60_dump_clk_registers()
776 DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n", in dcn60_dump_clk_registers()
777 regs_and_bypass->dcfclk, in dcn60_dump_clk_registers()
795 DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", in dcn60_dump_clk_registers()
912 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - " in dcn60_auto_dpm_test_log()
928 clk_register_dump.dcfclk, in dcn60_auto_dpm_test_log()
1061 action->dcfclk.update = true; in dcn60_make_bandwidth_clocks_update_action()
1062 action->dcfclk.send_message = dcfclk_dpm_enabled; in dcn60_make_bandwidth_clocks_update_action()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h49 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
50 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
H A Ddcn35_clk_mgr.c617 // read dcfclk in dcn35_save_clk_registers_internal()
646 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; in dcn35_save_clk_registers()
670 DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n", in dcn35_save_clk_registers()
671 regs_and_bypass->dcfclk, in dcn35_save_clk_registers()
687 DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk", in dcn35_save_clk_registers()
1092 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */ in dcn35_clk_mgr_helper_populate_bw_params()
1104 …/* First search defaults for the clocks we don't read using closest lower or equal default dcfclk … in dcn35_clk_mgr_helper_populate_bw_params()
1123 /* Dcfclk and Fclk are tied, but at a different ratio */ in dcn35_clk_mgr_helper_populate_bw_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core_structs.h703 …heck stage will figure the min DCFCLK freq to support the given display configuration. User can te…
827 …ommended DCFCLK freq; calculated by DML. If UseMinimumRequiredDCFCLK is not set; then it will be j…
834 …dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max c… member
1148 dml_float_t Dcfclk; member
1336 dml_float_t DCFCLK; member
1532 dml_float_t DCFCLK; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2305 …// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array in dcn30_update_bw_bounding_box()
2309 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates in dcn30_update_bw_bounding_box()
2322 // Calculate optimal dcfclk for each uclk in dcn30_update_bw_bounding_box()
2333 // Calculate optimal uclk for each dcfclk sta target in dcn30_update_bw_bounding_box()
2343 * all the optimal DCFCLK for each UCLK is lower than the smallest DCFCLK STA in dcn30_update_bw_bounding_box()
2344 * target, we need to populate the optimal UCLK for each DCFCLK STA target to in dcn30_update_bw_bounding_box()
2357 // create the final dcfclk and uclk table in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h214 * reader drain clk = dcfclk
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c662 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */ in dcn314_clk_mgr_helper_populate_bw_params()
676 …/* First search defaults for the clocks we don't read using closest lower or equal default dcfclk … in dcn314_clk_mgr_helper_populate_bw_params()
/linux/Documentation/gpu/amdgpu/display/
H A Dpipeline_4k_no_split.svg896 …ize:4.93888903px;stroke-width:0.16370411;text-anchor:middle;text-align:center">DCFCLK</tspan><tspan
H A Dpipeline_4k_split.svg1000 …ize:4.93888903px;stroke-width:0.16370411;text-anchor:middle;text-align:center">DCFCLK</tspan><tspan
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1884 …// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calcula… in dcn314_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1941 …// Disable DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX to set min dcfclk in calcula… in dcn31_validate_bandwidth()