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Searched +full:cx92755 +full:- +full:usart (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/serial/
H A Dcnxt,cx92755-usart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/cnxt,cx92755-usart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor USART
10 - Baruch Siach <baruch@tkos.co.il>
13 Note: this binding is only applicable for using the USART peripheral as UART.
14 USART also support synchronous serial protocols like SPI and I2S.
18 - $ref: /schemas/serial/serial.yaml#
22 const: cnxt,cx92755-usart
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/linux/arch/arm/boot/dts/cnxt/
H A Dcx92755.dtsi2 * Device Tree Include file for the Conexant Digicolor CX92755 SoC
8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "cnxt,cx92755";
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dcnxt,cx92755-pinctrl.txt1 Conexant Digicolor CX92755 General Purpose Pin Mapping
4 modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
25 #gpio-cells = <2>;
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/linux/drivers/tty/serial/
H A Ddigicolor-usart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Conexant Digicolor serial ports (USART)
85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
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