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Searched +full:cx92755 +full:- +full:timer (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/timer/
H A Dcnxt,cx92755-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cnxt,cx92755-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor SoCs Timer Controller
10 - Baruch Siach <baruch@tkos.co.il>
14 const: cnxt,cx92755-timer
20 description: Contains 8 interrupts, one for each timer
22 - description: interrupt for timer 0
23 - description: interrupt for timer 1
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/linux/arch/arm/boot/dts/cnxt/
H A Dcx92755.dtsi2 * Device Tree Include file for the Conexant Digicolor CX92755 SoC
8 * This file is dual-licensed: you can use it either under the terms
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "cnxt,cx92755";
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a8";
65 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dcnxt,cx92755-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cnxt,cx92755-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor SoCs Watchdog timer
12 timer counters. The first timer (called "Timer A") is the only one that can be
16 - Baruch Siach <baruch@tkos.co.il>
19 - $ref: watchdog.yaml#
23 const: cnxt,cx92755-wdt
32 - compatible
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/linux/drivers/clocksource/
H A Dtimer-digicolor.c1 // SPDX-License-Identifier: GPL-2.0
3 * Conexant Digicolor timer driver
14 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 * Conexant Digicolor SoCs have 8 configurable timers, named from "Timer A" to
19 * "Timer H". Timer A is the only one with watchdog support, so it is dedicated
20 * to the watchdog driver. This driver uses Timer B for sched_clock(), and
21 * Timer C for clockevents.
72 writeb(CONTROL_DISABLE, dt->base + CONTROL(dt->timer_id)); in dc_timer_disable()
78 writeb(CONTROL_ENABLE | mode, dt->base + CONTROL(dt->timer_id)); in dc_timer_enable()
85 writel(count, dt->base + COUNT(dt->timer_id)); in dc_timer_set_count()
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/linux/drivers/watchdog/
H A Ddigicolor_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
38 spin_lock_irqsave(&wdt->lock, flags); in dc_wdt_set()
40 writel_relaxed(0, wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
41 writel_relaxed(ticks, wdt->base + TIMER_A_COUNT); in dc_wdt_set()
43 wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
45 spin_unlock_irqrestore(&wdt->lock, flags); in dc_wdt_set()
64 dc_wdt_set(wdt, wdog->timeout * clk_get_rate(wdt->clk)); in dc_wdt_start()
73 writel_relaxed(0, wdt->base + TIMER_A_CONTROL); in dc_wdt_stop()
82 dc_wdt_set(wdt, t * clk_get_rate(wdt->clk)); in dc_wdt_set_timeout()
83 wdog->timeout = t; in dc_wdt_set_timeout()
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/linux/drivers/rtc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
141 once-per-second update interrupts, used for synchronization.
159 will be called rtc-test.
173 will be called rtc-88pm860x.
183 will be called rtc-88pm80x.
193 will be called rtc-88pm886.
197 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"
200 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.
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