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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dvctrl-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/vctrl-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Voltage controlled regulators
10 - Heiko Stuebner <heiko@sntech.de>
13 - $ref: regulator.yaml#
17 const: vctrl-regulator
19 ctrl-supply:
20 description: Regulator supplying the control voltage
[all …]
H A Dvctrl.txt1 Bindings for Voltage controlled regulators
5 ---------
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-gru-kevin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Kevin Rev 6+ board device tree source
5 * Copyright 2016-2017 Google, Inc
8 /dts-v1/;
9 #include "rk3399-gru-chromebook.dtsi"
10 #include <dt-bindings/input/linux-event-codes.h>
13 * Kevin-specific things
21 compatible = "google,kevin-rev15", "google,kevin-rev14",
22 "google,kevin-rev13", "google,kevin-rev12",
23 "google,kevin-rev11", "google,kevin-rev10",
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H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: regulator-ppvar-sys {
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H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
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H A Drk3566-powkiddy-rk2023.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/soc/rockchip,vop2.h>
13 chassis-type = "handset";
21 adc-joystick {
22 compatible = "adc-joystick";
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H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
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H A Drk3566-powkiddy-x55.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/soc/rockchip,vop2.h>
14 chassis-type = "handset";
25 stdout-path = "serial2:1500000n8";
28 adc_joystick: adc-joystick {
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H A Drk3588s-gameforce-ace.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include <dt-bindings/usb/pd.h>
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H A Drk3326-gameforce-chi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
16 chassis-type = "handset";
24 stdout-path = "serial2:115200n8";
27 adc_joystick: adc-joystick {
28 compatible = "adc-joystick";
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/freebsd/sys/arm/freescale/vybrid/
H A Dvf_adc.c1 /*-
28 * Vybrid Family 12-bit Analog to Digital Converter (ADC)
53 #define ADC_HC0 0x00 /* Ctrl reg for hardware triggers */
54 #define ADC_HC1 0x04 /* Ctrl reg for hardware triggers */
68 #define CFG_REFSEL_M 0x3 /* Voltage Reference Select Mask */
69 #define CFG_REFSEL_S 11 /* Voltage Reference Select Shift */
73 #define CFG_ADLPC (1 << 7) /* Low-Power Configuration */
79 #define CFG_MODE_12 0x2 /* 12-bit mode */
88 #define GC_ACREN (1 << 2) /* Compare Function Range En */
121 { -1, 0 }
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h1 /*-
2 * SPDX-License-Identifier: ISC
29 * PCI/PCIe-Gen1 DMA Constants
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
36 #define BHND_PCIE_DMA32_MASK BHND_PCIE_SBTOPCI2_MASK /**< PCIe-Gen1 DMA32 translation mask */
38 #define BHND_PCIE_DMA64_TRANSLATION _BHND_PCIE_DMA64(TRANSLATION) /**< PCIe-Gen1 DMA64 address tran…
39 #define BHND_PCIE_DMA64_MASK _BHND_PCIE_DMA64(MASK) /**< PCIe-Gen1 DMA64 translation mask */
76 /* BHND_PCI_ARB_CTL - ParkID (>= rev8) */
138 * PCIe-Gen1 Core Registers
252 #define BHND_PCIE_DLLP_LCREG_PCIPM_EN 0x40 /* Enable PCI-PM power management */
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/illumos-gate/usr/src/uts/common/io/iwk/
H A Diwk_hw.h21 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
41 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
46 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
98 * TFDB Area - TFDs buffer table
104 * channels 0 - 8
110 * TFDIB Area - TFD Immediate Buffer
116 * channels 0 - 10
148 * TRB Area - Transmit Request Buffers
154 * channels 0 - 8
[all …]
/freebsd/sys/dev/pccbb/
H A Dpccbb.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2000-2001 Jonathan Chen All rights reserved.
5 * Copyright (c) 2002-2004 M. Warner Losh <imp@FreeBSD.org>
30 /*-
65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
137 "Starting ioport for 16-bit cards");
142 "Starting ioport for 32-bit cards");
178 SLIST_FOREACH(rle, &sc->rl, link) { in cbb_remove_res()
179 if (rle->res == res) { in cbb_remove_res()
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/illumos-gate/usr/src/uts/common/sys/
H A Dsmbios_impl.h95 uint8_t smbsi_wakeup; /* wake-up type */
128 uint8_t smbch_bustate; /* boot-up state */
132 uint32_t smbch_oemdata; /* OEM-specific data */
171 uint8_t smbpr_voltage; /* voltage */
395 uint16_t smbmdev_minvolt; /* minimum voltage */
396 uint16_t smbmdev_maxvolt; /* maximum voltage */
397 uint16_t smbmdev_confvolt; /* configured voltage */
406 uint64_t smbmdev_nvsize; /* non-volatile memory size */
457 uint16_t smbbat_volt; /* design voltage in mV */
464 uint32_t smbbat_oemdata; /* OEM-specific data */
[all …]
H A Dsmbios.h69 uint8_t smbe_format[5]; /* entry point revision-specific data */
79 * The 64-bit SMBIOS 3.0 Entry Point. See DSP0134 5.2.2 for more information.
126 #define SMB_TYPE_OBDEVS 10 /* on-board devices (O) */
134 #define SMB_TYPE_MEMERR32 18 /* 32-bit memory error information */
137 #define SMB_TYPE_POINTDEV 21 /* built-in pointing device */
142 #define SMB_TYPE_VPROBE 26 /* voltage probe */
146 #define SMB_TYPE_OOBRA 30 /* out-of-band remote access facility */
149 #define SMB_TYPE_MEMERR64 33 /* 64-bit memory error information */
157 #define SMB_TYPE_OBDEVEXT 41 /* on-board device extended info */
166 #define SMB_TYPE_OEM_LO 128 /* start of OEM-specific type range */
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos4212-tab3.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos4412-ppmu-common.dtsi"
12 #include "exynos-mfc-reserved-memory.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
/illumos-gate/usr/src/uts/common/io/iwp/
H A Diwp_hw.h18 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
38 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
39 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
43 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
95 * TFDB Area - TFDs buffer table
101 * channels 0 - 8
107 * TFDIB Area - TFD Immediate Buffer
113 * channels 0 - 10
145 * TRB Area - Transmit Request Buffers
151 * channels 0 - 8
[all …]
/illumos-gate/usr/src/uts/common/io/iwh/
H A Diwh_hw.h21 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
41 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
46 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
98 * TFDB Area - TFDs buffer table
104 * channels 0 - 8
110 * TFDIB Area - TFD Immediate Buffer
116 * channels 0 - 10
148 * TRB Area - Transmit Request Buffers
154 * channels 0 - 8
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
47 compatible = "arm,armv7-timer";
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/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_peu_hw.h230 * Master Data Parity Error - set if all the following conditions
234 * Fast Back-to-Back Capable (N/A in PCIE)
236 * Capabilities List - presence of extended capability item.
239 * Fast Back-to-Back Enable (N/A in PCIE)
244 * The device can issue Memory Write-and-Invalidate commands (N/A
346 * Multi-Function Device: dbi writeable
374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0
432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX
489 * Description: Virtualization BAR0 - Previously for Hydra
566 * Subsystem ID as assigned by PCI-SIG : dbi writeable
[all …]
/illumos-gate/usr/src/uts/common/io/
H A Dpcic.c39 * clock-frequency bus clock frequency
41 * need-mult-irq need status IRQ for each pair of sockets
42 * disable-audio don't route audio signal to speaker
191 static int pcic_maxinst = -1;
233 /* bit patterns to select voltage levels */
279 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */
280 static int pcic_debounce_time = 200000; /* In micro-seconds */
482 *result = anp->an_dip; in pcic_getinfo()
617 * This function is called when the system is single-threaded at high
628 pcicdev_t *pcic = anp->an_private; in pcic_quiesce()
[all …]
/freebsd/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-
6794 int32_t voltage; global() member
6806 int32_t voltage; global() member
[all...]
/illumos-gate/usr/src/uts/common/io/cxgbe/t4nex/
H A Dt4_nexus.c15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
130 ASSERT(sc->dev == (dev_t)arg); in t4_devo_getinfo()
131 *rp = (void *)sc->dip; in t4_devo_getinfo()
147 "device-id", 0xffff); in t4_devo_probe()
204 sc->dip = dip; in t4_devo_attach()
205 sc->dev = makedevice(ddi_driver_major(dip), instance); in t4_devo_attach()
206 mutex_init(&sc->lock, NULL, MUTEX_DRIVER, NULL); in t4_devo_attach()
207 cv_init(&sc->cv, NULL, CV_DRIVER, NULL); in t4_devo_attach()
208 mutex_init(&sc->sfl_lock, NULL, MUTEX_DRIVER, NULL); in t4_devo_attach()
209 TAILQ_INIT(&sc->sfl); in t4_devo_attach()
[all …]

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