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/linux/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/
H A Dia_css_csc.host.c69 const struct sh_css_isp_csc_params *csc, in ia_css_cc_dump() argument
73 if (!csc) return; in ia_css_cc_dump()
77 csc->m_shift); in ia_css_cc_dump()
80 csc->m00); in ia_css_cc_dump()
83 csc->m01); in ia_css_cc_dump()
86 csc->m02); in ia_css_cc_dump()
89 csc->m10); in ia_css_cc_dump()
92 csc->m11); in ia_css_cc_dump()
95 csc->m12); in ia_css_cc_dump()
98 csc->m20); in ia_css_cc_dump()
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H A Dia_css_csc.host.h39 const struct sh_css_isp_csc_params *csc, unsigned int level,
44 const struct sh_css_isp_csc_params *csc,
/linux/drivers/media/platform/ti/vpe/
H A Dcsc.c20 #include "csc.h"
110 void csc_dump_regs(struct csc_data *csc) in csc_dump_regs() argument
112 struct device *dev = &csc->pdev->dev; in csc_dump_regs()
115 ioread32(csc->base + CSC_##r)) in csc_dump_regs()
117 dev_dbg(dev, "CSC Registers @ %pa:\n", &csc->res->start); in csc_dump_regs()
130 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5) in csc_set_coeff_bypass() argument
139 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0, in csc_set_coeff() argument
249 struct csc_data *csc; in csc_create() local
253 csc = devm_kzalloc(&pdev->dev, sizeof(*csc), GFP_KERNEL); in csc_create()
254 if (!csc) { in csc_create()
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H A DMakefile5 obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
10 ti-csc-y := csc.o
H A Dcsc.h58 void csc_dump_regs(struct csc_data *csc);
59 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5);
60 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0,
/linux/drivers/gpu/drm/i915/display/
H A Dintel_color.c104 * ILK+ csc matrix:
119 * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
172 static void intel_csc_clear(struct intel_csc_matrix *csc) in intel_csc_clear() argument
174 memset(csc, 0, sizeof(*csc)); in intel_csc_clear()
209 const struct intel_csc_matrix *csc) in ilk_update_pipe_csc() argument
214 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]); in ilk_update_pipe_csc()
215 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]); in ilk_update_pipe_csc()
216 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]); in ilk_update_pipe_csc()
219 csc->coeff[0] << 16 | csc->coeff[1]); in ilk_update_pipe_csc()
221 csc->coeff[2] << 16); in ilk_update_pipe_csc()
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H A Dintel_crtc_state_dump.c151 const struct intel_csc_matrix *csc) in ilk_dump_csc() argument
156 csc->preoff[0], csc->preoff[1], csc->preoff[2]); in ilk_dump_csc()
160 csc->coeff[3 * i + 0], in ilk_dump_csc()
161 csc->coeff[3 * i + 1], in ilk_dump_csc()
162 csc->coeff[3 * i + 2]); in ilk_dump_csc()
168 csc->postoff[0], csc->postoff[1], csc->postoff[2]); in ilk_dump_csc()
173 const struct intel_csc_matrix *csc) in vlv_dump_csc() argument
179 csc->coeff[3 * i + 0], in vlv_dump_csc()
180 csc->coeff[3 * i + 1], in vlv_dump_csc()
181 csc->coeff[3 * i + 2]); in vlv_dump_csc()
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/linux/drivers/gpu/ipu-v3/
H A Dipu-ic-csc.c355 static int calc_csc_coeffs(struct ipu_ic_csc *csc) in calc_csc_coeffs() argument
360 tbl_idx = (QUANT_MAP(csc->in_cs.quant) << 1) | in calc_csc_coeffs()
361 QUANT_MAP(csc->out_cs.quant); in calc_csc_coeffs()
363 if (csc->in_cs.cs == csc->out_cs.cs) { in calc_csc_coeffs()
364 csc->params = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
372 switch (csc->out_cs.enc) { in calc_csc_coeffs()
374 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
378 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
385 csc->params = *params_tbl[tbl_idx]; in calc_csc_coeffs()
390 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc) in __ipu_ic_calc_csc() argument
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H A Dipu-ic.c175 const struct ipu_ic_csc *csc, in init_csc() argument
188 c = (const u16 (*)[3])csc->params.coeff; in init_csc()
189 a = (const u16 *)csc->params.offset; in init_csc()
195 param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) | in init_csc()
196 (csc->params.sat << 10); in init_csc()
398 const struct ipu_ic_csc *csc, in ipu_ic_task_init_rsc() argument
432 ic->in_cs = csc->in_cs; in ipu_ic_task_init_rsc()
433 ic->out_cs = csc->out_cs; in ipu_ic_task_init_rsc()
435 ret = init_csc(ic, csc, 0); in ipu_ic_task_init_rsc()
442 const struct ipu_ic_csc *csc, in ipu_ic_task_init() argument
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/linux/drivers/gpu/drm/tidss/
H A Dtidss_dispc.c1415 /* CSC */
1435 void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);
1446 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_offset_regval() argument
1449 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1450 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1451 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1457 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_yuv2rgb_regval() argument
1459 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1460 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1461 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
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/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_plane.c166 enum mdp4_pipe pipe, struct csc_cfg *csc) in mdp4_write_csc_config() argument
170 for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) { in mdp4_write_csc_config()
172 csc->matrix[i]); in mdp4_write_csc_config()
175 for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) { in mdp4_write_csc_config()
177 csc->pre_bias[i]); in mdp4_write_csc_config()
180 csc->post_bias[i]); in mdp4_write_csc_config()
183 for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) { in mdp4_write_csc_config()
185 csc->pre_clamp[i]); in mdp4_write_csc_config()
188 csc->post_clamp[i]); in mdp4_write_csc_config()
322 struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB); in mdp4_plane_mode_set() local
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/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-subdev-enum-mbus-code.rst118 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
125 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
132 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
139 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
146 ioctl with :ref:`V4L2_MBUS_FRAMEFMT_SET_CSC <mbus-framefmt-set-csc>` set.
H A Dvidioc-enum-fmt.rst201 :ref:`V4L2_PIX_FMT_FLAG_SET_CSC <v4l2-pix-fmt-flag-set-csc>` set.
208 :ref:`V4L2_PIX_FMT_FLAG_SET_CSC <v4l2-pix-fmt-flag-set-csc>` set.
215 :ref:`V4L2_PIX_FMT_FLAG_SET_CSC <v4l2-pix-fmt-flag-set-csc>` set.
222 :ref:`V4L2_PIX_FMT_FLAG_SET_CSC <v4l2-pix-fmt-flag-set-csc>` set.
229 :ref:`V4L2_PIX_FMT_FLAG_SET_CSC <v4l2-pix-fmt-flag-set-csc>` set.
/linux/Documentation/devicetree/bindings/media/
H A Dti,vpe.yaml26 - description: Color Space Conversion (CSC) register region
33 - const: csc
59 "csc",
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_cdm.c175 u32 csc = 0; in dpu_hw_cdm_enable() local
195 csc |= CDM_CSC10_OP_MODE_DST_FMT_YUV; in dpu_hw_cdm_enable()
196 csc &= ~CDM_CSC10_OP_MODE_SRC_FMT_YUV; in dpu_hw_cdm_enable()
197 csc |= CDM_CSC10_OP_MODE_EN; in dpu_hw_cdm_enable()
202 DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc); in dpu_hw_cdm_enable()
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dwndw.c136 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
164 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); in nv50_wndw_flush_set()
421 if (wndw->func->csc && asyh->state.ctm) { in nv50_wndw_atomic_check_lut()
423 wndw->func->csc(wndw, asyw, ctm); in nv50_wndw_atomic_check_lut()
424 asyw->csc.valid = true; in nv50_wndw_atomic_check_lut()
425 asyw->set.csc = true; in nv50_wndw_atomic_check_lut()
427 asyw->csc.valid = false; in nv50_wndw_atomic_check_lut()
428 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
509 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check()
608 asyw->csc = armw->csc; in nv50_wndw_atomic_duplicate_state()
H A Dbase907c.c144 u32 *val = &asyw->csc.matrix[j * 4 + i]; in base907c_csc()
146 * HW CSC does. Skip it. */ in base907c_csc()
181 NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]), in base907c_csc_set()
183 SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11); in base907c_csc_set()
198 .csc = base907c_csc,
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_csc.c51 * DE3 has a bit different CSC units. Factors are in two's complement format.
62 * Please note that above formula is true only for Blender CSC. Other DE3 CSC
138 DRM_WARN("Wrong CSC mode specified.\n"); in sun8i_csc_set_coefficients()
176 DRM_WARN("Wrong CSC mode specified.\n"); in sun8i_de3_ccsc_set_coefficients()
/linux/drivers/staging/media/deprecated/atmel/
H A Datmel-sama7g5-isc.c9 * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
20 * CSC: Programmable color space conversion
215 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
217 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
219 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
221 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
223 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
225 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
429 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
H A Datmel-sama5d2-isc.c11 * Sensor-->PFE-->WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB-->RLP-->DMA
19 * CSC: Programmable color space conversion
202 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
204 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
206 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
208 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
210 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
212 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
440 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in atmel_isc_probe()
/linux/drivers/media/platform/microchip/
H A Dmicrochip-sama7g5-isc.c9 * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
20 * CSC: Programmable color space conversion
235 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
237 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
239 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
241 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
243 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
245 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
448 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
H A Dmicrochip-sama5d2-isc.c11 * Sensor-->PFE-->WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB-->RLP-->DMA
19 * CSC: Programmable color space conversion
222 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
224 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
226 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
228 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
230 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
232 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
459 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in microchip_isc_probe()
/linux/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2711-hdmi.yaml26 - description: CSC register range
38 - const: csc
132 "csc",
/linux/arch/powerpc/boot/
H A Dmvme5100.c5 * Author: Stephen Chivers <schivers@csc.com>
7 * Copyright 2013 CSC Australia Pty. Ltd.
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_plane.c501 struct csc_cfg *csc) in csc_enable() argument
503 uint32_t i, mode = 0; /* RGB, no CSC */ in csc_enable()
506 if (unlikely(!csc)) in csc_enable()
509 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) in csc_enable()
511 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) in csc_enable()
516 matrix = csc->matrix; in csc_enable()
532 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { in csc_enable()
533 uint32_t *pre_clamp = csc->pre_clamp; in csc_enable()
534 uint32_t *post_clamp = csc->post_clamp; in csc_enable()
545 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); in csc_enable()
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