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/illumos-gate/usr/src/uts/intel/io/coretemp/
H A Dcoretemp.c18 * Intel CPU Thermal sensor driver
22 * temperature sensors exist on a per-core basis and optionally on a per-package
27 * down the datasheet. Unfortunately, the values here are often on a per-brand
31 * The temperature is exposed through /dev and uses a semi-standard sensor
32 * framework. We expose one minor node per CPU core and one minor node per CPU
33 * package, if that is supported. Reads are rate-limited in the driver at 100ms
132 * fixed for use outside of a panic-like context.
137 id_t cpu = cmi_hdl_logical_id(hdl); in coretemp_rdmsr() local
140 ASSERT(MUTEX_HELD(&ct->coretemp_mutex)); in coretemp_rdmsr()
142 if (CPU->cpu_id == cpu) { in coretemp_rdmsr()
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/illumos-gate/usr/src/uts/intel/sys/amdzen/
H A Dthm.h23 * This header covers the SMU's (system management unit) thermal block. The SMU,
28 * The thermal block SMN registers are generally shadows or calculated
30 * features that exist within the SOC. Only a subset of the overall thermal
34 * (SB-TSI), which is consumed by the service processor on a system board that
35 * maintains a thermal loop.
37 * Note, CCDs have their own separate thermal block, SMU::THMCCD.
45 * SMU::THM registers, per-die. This functional unit is present in all Zen CPUs
53 * SMU::THM::THM_TCON_CUR_TMP -- the primary thermal sensor in a given die. This
67 #define THM_CURTEMP_RANGE_ADJ (-49)
79 * SMU::THM::THM_DIEX_TEMP -- this is a per-die measurement that comes from the
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/illumos-gate/usr/src/uts/intel/io/acpica/
H A Dahids.c3 * Module Name: ahids - Table of ACPI/PNP _HID/_CID values
8 * Copyright (C) 2000 - 2016, Intel Corp.
22 * 3. Neither the names of the above-listed copyright holders nor the names
125 {"INT33FB", "MIPI-CSI Camera Sensor OV2722"},
130 {"INT3401", "Intel Extended Thermal Model CPU"},
132 {"INT3406", "Intel Dynamic Platform & Thermal Framework Display Participant"},
140 {"INVN6500", "InvenSense MPU-6500 Six Axis Gyroscope and Accelerometer"},
141 {"LNXCPU", "Linux Logical CPU"},
146 {"LNXTHERM", "ACPI Thermal Zone"},
152 {"PNP0000", "8259-compatible Programmable Interrupt Controller"},
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/illumos-gate/usr/src/man/man4d/
H A Dsmntemp.4d22 .Pa /dev/sensors/temperature/cpu/*
29 on Zen 1-5 processors
36 There is no per-core temperature sensor available.
43 A value of 95 indicates that thermal throttling should be occurring and a value
44 of 100 indicates that the chip will hit its thermal limit and shut down if no
64 .%B Open-Source Register Reference For AMD Family 17h Processors Models 00h-2Fh
/illumos-gate/usr/src/uts/i86pc/os/cpupm/
H A Dcpupm_amd.c29 * AMD-specific CPU power management support.
31 * And, a brief history of AMD CPU power management. Or, "Why you care about CPU
36 * In the early 2000s, AMD shipped a feature called PowerNow! in the K6 era -
37 * K6-2E+ and K6-III+ cores, according to "AMD PowerNow! Technology Dynamically
40 * that is very similar to ACPI P-states. That is, selectable core voltage and
41 * frequency levels, with default "power-saver" and "high-performance" modes
42 * that are reflective of Pmin and Pmax on a 2024-era AMD processor.
54 * * introduces the notion of power-governed turbo boost
56 * Somewhere in the K10 era, AMD also introduced C-state support, allowing cores
57 * to be put into low-power idle states when not used. Some articles from
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H A Dcpupm_throttle.c40 "Generic ACPI T-state Support",
85 switch (ptc_ctrl->cr_addrspace_id) { in write_ctrl()
88 * Read current thermal state because reserved bits must be in write_ctrl()
91 * Bits 3:1 => On-Demand Clock Modulation Duty Cycle in write_ctrl()
92 * Bit 4 => On-Demand Clock Modulation Enable in write_ctrl()
93 * Left shift ctrl by 1 to allign with bits 1-4 of MSR in write_ctrl()
102 ret = cpu_acpi_write_port(ptc_ctrl->cr_address, ctrl, in write_ctrl()
103 ptc_ctrl->cr_width); in write_ctrl()
108 ptc_ctrl->cr_addrspace_id); in write_ctrl()
110 ret = -1; in write_ctrl()
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H A Dcpupm_mach.c47 * This callback is used to build the PPM CPU domains once
48 * a CPU device has been started. The callback is initialized
55 * This callback is used to remove CPU from the PPM CPU domains
56 * when the cpu driver is detached. The callback is initialized
57 * by the PPM driver to point to a routine that will remove CPU
63 * This callback is used to redefine the topspeed for a CPU device.
66 * that will redefine the topspeed for all devices in a CPU domain.
68 * is received by the CPU driver.
73 * This callback is used by the PPM driver to call into the CPU driver
74 * to find a CPU's current topspeed (i.e., it's current ACPI _PPC value).
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/illumos-gate/usr/src/uts/intel/io/pchtemp/
H A Dpchtemp.c18 * Intel Platform Controller Hub (PCH) Thermal Sensor Driver
22 * the CPU. While it existed prior to the Nehalem generation, it was previously
28 * thermal sensor which gives us the ability to read the temperature sensor that
36 * - Intel 8 Series PCH
37 * - Intel 9 Series and Broadwell Mobile Low Power PCH
38 * - Intel C610 Series and X99 PCH
39 * - Intel C620 Series PCH
40 * - Intel 100 Series PCH
41 * - Intel 200 Series and Z730 PCH
42 * - Intel Sunrise Point-LP (Kaby Lake-U) PCH
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/illumos-gate/usr/src/cmd/acpi/common/
H A Dahids.c3 * Module Name: ahids - Table of ACPI/PNP _HID/_CID values
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
234 {"INT33FB", "MIPI-CSI Camera Sensor OV2722"},
239 {"INT3401", "Intel Extended Thermal Model CPU"},
241 {"INT3406", "Intel Dynamic Platform & Thermal Framework Display Participant"},
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/illumos-gate/usr/src/uts/intel/sys/
H A Dx86_archext.h31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
59 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
68 /* 0x400 - reserved */
75 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
78 /* 0x100000 - reserved */
85 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
87 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
97 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
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/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c53 dev_info_t *dip = pci_p->pci_dip; in ib_create()
63 pci_p->pci_ib_p = ib_p; in ib_create()
64 ib_p->ib_pci_p = pci_p; in ib_create()
72 ib_p->ib_slot_clear_intr_regs = in ib_create()
74 ib_p->ib_intr_retry_timer_reg = in ib_create()
76 ib_p->ib_slot_intr_state_diag_reg = in ib_create()
78 ib_p->ib_obio_intr_state_diag_reg = in ib_create()
82 ib_p->ib_upa_imr[0] = (volatile uint64_t *) in ib_create()
84 ib_p->ib_upa_imr[1] = (volatile uint64_t *) in ib_create()
89 ib_p->ib_slot_intr_map_regs, ib_p->ib_obio_intr_map_regs); in ib_create()
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H A Dpcipsy.c74 cmn_p = get_pci_common_soft_state(pci_p->pci_id); in pci_obj_setup()
76 uint_t id = pci_p->pci_id; in pci_obj_setup()
82 cmn_p->pci_common_id = id; in pci_obj_setup()
85 ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); in pci_obj_setup()
86 if (cmn_p->pci_p[pci_p->pci_side]) { in pci_obj_setup()
88 pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); in pci_obj_setup()
89 ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); in pci_obj_setup()
92 cmn_p->pci_p[pci_p->pci_side] = pci_p; in pci_obj_setup()
93 pci_p->pci_common_p = cmn_p; in pci_obj_setup()
95 if (cmn_p->pci_common_refcnt == 0) { in pci_obj_setup()
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H A Dpci_space.c60 * "interrupt-priorities" property. This property is an array of integer
63 * "interrupt-priorities" value was (5, 12), the handler for the first
64 * interrupt would run at cpu priority 5 and the second at priority 12.
100 * 1234181 - obp should set latency timer registers in pci
113 * 1235094 - need workarounds on positron nexus drivers to set cache
137 uint_t pci_sbh_error_intr_enable = (uint_t)-1;
138 uint_t pci_mmu_error_intr_enable = (uint_t)-1;
139 uint_t pci_stream_buf_enable = (uint_t)-1;
143 uint_t pci_enable_retry_arb = (uint_t)-1;
145 uint_t pci_bus_parking_enable = (uint_t)-1;
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H A Dpci_intr.c67 * devices only. A different scheme will be used for plug-in cards.
74 0, 0, 0, 0, /* 0x00 - 0x03: bus A slot 0 int#A, B, C, D */
75 0, 0, 0, 0, /* 0x04 - 0x07: bus A slot 1 int#A, B, C, D */
76 0, 0, 0, 0, /* 0x08 - 0x0B: unused */
77 0, 0, 0, 0, /* 0x0C - 0x0F: unused */
79 0, 0, 0, 0, /* 0x10 - 0x13: bus B slot 0 int#A, B, C, D */
80 0, 0, 0, 0, /* 0x14 - 0x17: bus B slot 1 int#A, B, C, D */
81 0, 0, 0, 0, /* 0x18 - 0x1B: bus B slot 2 int#A, B, C, D */
82 4, 0, 0, 0, /* 0x1C - 0x1F: bus B slot 3 int#A, B, C, D */
92 14, /* 0x28: thermal warning */
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/illumos-gate/usr/src/uts/intel/io/amdzen/
H A Dsmntemp.c21 * ----------
23 * ----------
29 * one that comes up most inside of devices like a CPU as it looks at the
35 * that have some amount of post-processing applied to them from different
39 * primary thing that the CPU exposes and is used for overall health is quite
45 * 1) At a value of 95, the CPU will begin internal thermal throttling.
46 * 2) At a value of 100, after some period of time the CPU will shutdown. This
48 * the CPU socket.
56 * earlier life of this driver. The addition of the various CCD-specific sensors
59 * -------------------------------------
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/illumos-gate/usr/src/uts/i86pc/io/
H A Dcpudrv_mach.c31 * CPU power management driver support for i86pc.
47 * the highest power level is cpupm->num_spd). The x86 modules get
50 * is (cpupm->num_spd - 1) and the highest power level is 0). So to
52 * simply subtract our driver power level from cpupm->num_spd. Likewise,
54 * subtract the ACPI power level from cpupm->num_spd.
56 #define PM_2_PLAT_LEVEL(cpupm, pm_level) (cpupm->num_spd - pm_level)
57 #define PLAT_2_PM_LEVEL(cpupm, plat_level) (cpupm->num_spd - plat_level)
60 * Change CPU speed using interface provided by module.
65 cpu_t *cp = cpudsp->cp; in cpudrv_change_speed()
67 (cpupm_mach_state_t *)cp->cpu_m.mcpu_pm_mach_state; in cpudrv_change_speed()
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/illumos-gate/usr/src/man/man9e/
H A Dksensor.9e23 .Sy Volatile -
41 .Bl -tag -width Ds
52 For example, a value of -2 would indicate that you'd need to multiply the value
58 read from the sensor is in degrees, and is accurate to +/-5 degrees would set
62 If the sensor was accurate to +/-1 degree, then it'd have a precision of 2.
74 .Bl -tag -width Dv
105 where 100 indicates that a thermal shutdown is imminent.
118 .Bl -tag -width Dv
166 .Bl -tag -width Ds
168 Indicates that this is a temperature sensor that relates to the CPU, whether the
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/illumos-gate/usr/src/lib/libprtdiag_psr/sparc/daktari/common/
H A Ddaktari.c72 #define MULTIPLE_BITS_SET(x) ((x)&((x)-1))
138 Board_node *bnode = tree->bd_list; in disp_fail_parts()
144 pnode = find_failed_node(bnode->nodes); in disp_fail_parts()
173 if (bnode->board_type == CPU_BOARD) { in disp_fail_parts()
174 board_type = "CPU"; in disp_fail_parts()
181 bnode->board_num); in disp_fail_parts()
190 * Determine whether FRU is CPU module, system in disp_fail_parts()
199 } else if (((name = get_node_name(pnode->parent)) != in disp_fail_parts()
207 (strstr(type, "cpu"))) { in disp_fail_parts()
216 bnode->board_num); in disp_fail_parts()
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/illumos-gate/usr/src/uts/sun4u/javelin/io/
H A Denvctrltwo.c136 static int psok[2] = {-1, -1};
137 static int pspr[2] = {-1, -1};
158 * green = OK - no action needed
159 * yellow = warning - display warning message and poll faster
160 * red = critical - shutdown system
227 &mod_driverops, /* type of module - driver */
296 mutex_enter(&unitp->umutex); in envctrl_attach()
297 if (!unitp->suspended) { in envctrl_attach()
298 mutex_exit(&unitp->umutex); in envctrl_attach()
301 unitp->suspended = 0; in envctrl_attach()
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/illumos-gate/usr/src/cmd/fm/dicts/
H A DINTEL.po24 # DO NOT EDIT -- this file is generated by the Event Registry.
27 # code: INTEL-8000-1J
28 # keys: fault.cpu.intel.internal
30 msgid "INTEL-8000-1J.type"
32 msgid "INTEL-8000-1J.severity"
34 msgid "INTEL-8000-1J.description"
35 msgstr "An internal error has been encountered on this cpu. Refer to %s for more information."
36 msgid "INTEL-8000-1J.response"
37 msgstr "The system will attempt to offline this cpu to remove it from service."
38 msgid "INTEL-8000-1J.impact"
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/illumos-gate/usr/src/boot/sys/x86/include/
H A Dspecialreg.h1 /*-
52 #define CR0_NW 0x20000000 /* Not Write-through */
62 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
72 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */
76 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */
84 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
183 * Important bits in the Thermal and Power Management flags
274 * MWAIT cpu power states. Lower 4 bits are sub-states.
302 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
376 * Model-specific registers for the i386 family
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/illumos-gate/usr/src/uts/intel/io/vmm/
H A Dvmm_cpuid.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 /* This file is dual-licensed; see usr/src/contrib/bhyve/LICENSE */
63 * All CPUID instruction exits are handled by the in-kernel emulation.
65 * ----------------
67 * ----------------
70 * and/or generate CPUID results based on what was reported by the host CPU, as
71 * well as attributes of the VM (such as CPU topology, and enabled features).
72 * This is largely adequate to expose CPU capabilities to the guest in manner
75 * ------------------------------
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/illumos-gate/usr/src/contrib/bhyve/x86/
H A Dapicreg.h1 /*-
25 * $FreeBSD: head/sys/x86/include/apicreg.h 259140 2013-12-09 21:08:52Z jhb $
36 * Pentium P54C+ Built-in APIC
39 * Base Address of Built-in APIC in memory location
61 * 100 ISR 000-031 R
62 * 110 ISR 032-063 R
63 * 120 ISR 064-095 R
64 * 130 ISR 095-128 R
65 * 140 ISR 128-159 R
66 * 150 ISR 160-191 R
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/illumos-gate/usr/src/uts/i86pc/io/fipe/
H A Dfipe_pm.c28 #include <sys/cpu.h>
91 #define FIPE_PROFILE_FIELD(field) (fipe_profile_curr->field)
187 #define FIPE_CPU_STATE_PAD (128 - \
188 2 * sizeof (boolean_t) - 4 * sizeof (hrtime_t) - \
189 2 * sizeof (uint64_t) - 2 * sizeof (uint32_t))
191 /* Per-CPU status. */
292 * 2) MC works in S-CLTT mode
297 /* Enable OLTT/disable S-CLTT mode */ in fipe_mc_change()
303 * Set S-CLTT low throttling to desired value. The lower value, in fipe_mc_change()
307 /* Enable S-CLTT/disable OLTT mode */ in fipe_mc_change()
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/illumos-gate/usr/src/uts/sun4u/sys/
H A Denvctrl_ue450.h40 * to the UltraEnterprise-450 (aka. Ultra-4) platform.
48 #define ENVCTRL_TAZBLKBRDCPU_STRING "SUNW,UltraSPARC-II"
54 #define S1 &unitp->bus_ctl_regs->s1
55 #define S0 &unitp->bus_ctl_regs->s0
88 * 0x00 - 0x0F. 0x00 is the CSR and MUST be addressed
109 #define CPU_AMB_RISE 20 /* cpu runs avg of 20 above amb */
110 #define PS_AMB_RISE 30 /* cpu runs avg of 30 above amb */
149 * MSB -------------------------------------> LSB
150 * ----------------------------------------------
152 * ----------------------------------------------
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