| /titanic_41/usr/src/man/man4/ |
| H A D | power.conf.4 | 8 power.conf \- Power Management configuration information file
25 allowed by this file. For ease-of-use, it is recommended that you use
34 power when the device is idle.
45 \fBpm-components\fR property describes the Power Management model of a device
46 driver to the Power Management framework. See \fBpm-components\fR(9P) for more
50 When a component has been idle at a given power level for its threshold time,
53 component is power-managed independently.
59 have all been idle for the system's idleness threshold. The default system
60 idleness threshold is determined by the applicable United States Environmental
69 system-threshold \fIthreshold\fR
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| /illumos-gate/usr/src/man/man5/ |
| H A D | power.conf.5 | 8 power.conf \- Power Management configuration information file
25 power when the device is idle.
34 \fBpm-components\fR property describes the Power Management model of a device
35 driver to the Power Management framework. See \fBpm-components\fR(9P) for more
39 When a component has been idle at a given power level for its threshold time,
42 component is power-managed independently.
48 have all been idle for the system's idleness threshold. The default system
49 idleness threshold is determined by the applicable United States Environmental
58 system-threshold \fIthreshold\fR
65 system-threshold \fBalways-on\fR
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| /illumos-gate/usr/src/uts/common/os/ |
| H A D | cpu_pm.c | 32 * Solaris Event Based CPU Power Manager
34 * This file implements platform independent event based CPU power management.
36 * query the platform to determine if the CPU belongs to any power management
37 * domains. That is, sets of CPUs that share power management states.
44 * Idle Power Management domains can enter power savings states when they are
45 * unutilized. These states allow the Operating System to trade off power
46 * for performance (in the form of latency to transition from the idle state
49 * For each active and idle power domain the CMT subsystem instantiates, a
58 * Under the "elastic" CPUPM policy, when the utilization rises, the CPU power
60 * power consuming) state. When the domain becomes idle (utilization at zero),
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| H A D | msacct.c | 40 * Mega-theory block comment:
42 * Microstate accounting uses finite states and the transitions between these
43 * states to measure timing and accounting information. The state information
45 * cpu microstate accounting). In each case, these accounting mechanisms use
46 * states and transitions to measure time spent in each state instead of
47 * clock-based sampling methodologies.
51 * states. Transitions from a sleeping state (LMS_SLEEP and LMS_STOPPED) occur
56 * thread has spent waiting on run-queues in its lifetime.
58 * For cpu microstate accounting:
59 * Cpu microstate accounting is similar to the microstate accounting for threads
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| H A D | softint.c | 49 * when CPU is stuck due to high interrupt load and can't execute callbacks.
50 * State diagram is as follows :-
52 * - Upper half which is same as old state machine
53 * (IDLE->PEND->DRAIN->IDLE)
55 * - Lower half which steals the entries from softcall queue and execute
57 * is fired on a different CPU by sending a cross-call.
59 * Starting state is IDLE.
68 * IDLE--------------------->PEND--------------------->DRAIN
79 * |<-----------------------STEAL STEAL
87 * Edge (a)->(b)->(c) are same as old state machine and these
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| /titanic_41/usr/src/uts/common/os/ |
| H A D | cpu_pm.c | 32 * Solaris Event Based CPU Power Manager
34 * This file implements platform independent event based CPU power management.
36 * query the platform to determine if the CPU belongs to any power management
37 * domains. That is, sets of CPUs that share power management states.
44 * Idle Power Management domains can enter power savings states when they are
45 * unutilized. These states allow the Operating System to trade off power
46 * for performance (in the form of latency to transition from the idle state
49 * For each active and idle power domain the CMT subsystem instantiates, a
58 * Under the "elastic" CPUPM policy, when the utilization rises, the CPU power
60 * power consuming) state. When the domain becomes idle (utilization at zero),
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| H A D | msacct.c | 39 * Mega-theory block comment:
41 * Microstate accounting uses finite states and the transitions between these
42 * states to measure timing and accounting information. The state information
44 * cpu microstate accounting). In each case, these accounting mechanisms use
45 * states and transitions to measure time spent in each state instead of
46 * clock-based sampling methodologies.
50 * states. Transitions from a sleeping state (LMS_SLEEP and LMS_STOPPED) occur
55 * thread has spent waiting on run-queues in its lifetime.
57 * For cpu microstate accounting:
58 * Cpu microstate accounting is similar to the microstate accounting for threads
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| H A D | softint.c | 49 * when CPU is stuck due to high interrupt load and can't execute callbacks.
50 * State diagram is as follows :-
52 * - Upper half which is same as old state machine
53 * (IDLE->PEND->DRAIN->IDLE)
55 * - Lower half which steals the entries from softcall queue and execute
57 * is fired on a different CPU by sending a cross-call.
59 * Starting state is IDLE.
68 * IDLE--------------------->PEND--------------------->DRAIN
79 * |<-----------------------STEAL STEAL
87 * Edge (a)->(b)->(c) are same as old state machine and these
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| /illumos-gate/usr/src/uts/i86pc/os/cpupm/ |
| H A D | cpu_idle.c | 26 * Copyright (c) 2009-2010, Intel Corporation.
70 * the flag of always-running local APIC timer.
77 * Interfaces for modules implementing Intel's deep c-state.
80 "Generic ACPI C-state Support",
101 * kstat update function of the c-state info
106 cpu_acpi_cstate_t *cstate = ksp->ks_private; in cpu_idle_kstat_update()
112 if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { in cpu_idle_kstat_update()
115 } else if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_SYSTEM_IO) { in cpu_idle_kstat_update()
123 cpu_idle_kstat.cs_latency.value.ui32 = cstate->cs_latency; in cpu_idle_kstat_update()
124 cpu_idle_kstat.cs_power.value.ui32 = cstate->cs_power; in cpu_idle_kstat_update()
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| H A D | cpupm_mach.c | 47 * This callback is used to build the PPM CPU domains once
48 * a CPU device has been started. The callback is initialized
55 * This callback is used to remove CPU from the PPM CPU domains
56 * when the cpu driver is detached. The callback is initialized
57 * by the PPM driver to point to a routine that will remove CPU
63 * This callback is used to redefine the topspeed for a CPU device.
66 * that will redefine the topspeed for all devices in a CPU domain.
68 * is received by the CPU driver.
73 * This callback is used by the PPM driver to call into the CPU driver
74 * to find a CPU's current topspeed (i.e., it's current ACPI _PPC value).
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| H A D | cpupm_amd.c | 29 * AMD-specific CPU power management support.
31 * And, a brief history of AMD CPU power management. Or, "Why you care about CPU
36 * In the early 2000s, AMD shipped a feature called PowerNow! in the K6 era -
37 * K6-2E+ and K6-III+ cores, according to "AMD PowerNow! Technology Dynamically
40 * that is very similar to ACPI P-states. That is, selectable core voltage and
41 * frequency levels, with default "power-saver" and "high-performance" modes
42 * that are reflective of Pmin and Pmax on a 2024-era AMD processor.
54 * * introduces the notion of power-governed turbo boost
56 * Somewhere in the K10 era, AMD also introduced C-state support, allowing cores
57 * to be put into low-power idle states when not used. Some articles from
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| /titanic_41/usr/src/uts/i86pc/os/cpupm/ |
| H A D | cpu_idle.c | 26 * Copyright (c) 2009-2010, Intel Corporation.
66 * the flag of always-running local APIC timer.
73 * Interfaces for modules implementing Intel's deep c-state.
76 "Generic ACPI C-state Support",
97 * kstat update function of the c-state info
102 cpu_acpi_cstate_t *cstate = ksp->ks_private; in cpu_idle_kstat_update()
108 if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { in cpu_idle_kstat_update()
111 } else if (cstate->cs_addrspace_id == ACPI_ADR_SPACE_SYSTEM_IO) { in cpu_idle_kstat_update()
119 cpu_idle_kstat.cs_latency.value.ui32 = cstate->cs_latency; in cpu_idle_kstat_update()
120 cpu_idle_kstat.cs_power.value.ui32 = cstate->cs_power; in cpu_idle_kstat_update()
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| H A D | cpupm_mach.c | 47 * This callback is used to build the PPM CPU domains once
48 * a CPU device has been started. The callback is initialized
55 * This callback is used to remove CPU from the PPM CPU domains
56 * when the cpu driver is detached. The callback is initialized
57 * by the PPM driver to point to a routine that will remove CPU
63 * This callback is used to redefine the topspeed for a CPU device.
66 * that will redefine the topspeed for all devices in a CPU domain.
68 * is received by the CPU driver.
73 * This callback is used by the PPM driver to call into the CPU driver
74 * to find a CPU's current topspeed (i.e., it's current ACPI _PPC value).
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| /illumos-gate/usr/src/uts/common/sys/ |
| H A D | cpu_pm.h | 41 * CPU Power Manager Policies
50 * Power Managable CPU Domain Types
54 CPUPM_DTYPE_IDLE /* Idle Power Domain */
68 * Possible states for the domain's transience governor
88 * CPU Power Domain State
96 * CPU Power Domain
100 cpupm_dtype_t cpd_type; /* Active or Idle */
101 cpupm_state_t *cpd_states; /* Available Power States */
103 uint_t cpd_nstates; /* Number of States */
107 int cpd_ti; /* transient idle history */
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| /titanic_41/usr/src/uts/common/sys/ |
| H A D | cpu_pm.h | 41 * CPU Power Manager Policies
50 * Power Managable CPU Domain Types
54 CPUPM_DTYPE_IDLE /* Idle Power Domain */
68 * Possible states for the domain's transience governor
88 * CPU Power Domain State
96 * CPU Power Domain
100 cpupm_dtype_t cpd_type; /* Active or Idle */
101 cpupm_state_t *cpd_states; /* Available Power States */
103 uint_t cpd_nstates; /* Number of States */
107 int cpd_ti; /* transient idle history */
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| /illumos-gate/usr/src/cmd/powertop/common/ |
| H A D | cpuidle.c | 20 * Boston, MA 02110-1301 USA
49 * Buffer containing DTrace program to track CPU idle state transitions
52 ":::idle-state-transition"
55 " self->start = timestamp;"
56 " self->state = arg0;"
59 ":::idle-state-transition"
60 "/arg0 == 0 && self->start/"
62 " @number[self->state] = count();"
63 " @times[self->state] = sum(timestamp - self->start);"
64 " self->start = 0;"
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| /titanic_41/usr/src/cmd/powertop/common/ |
| H A D | cpuidle.c | 20 * Boston, MA 02110-1301 USA
49 * Buffer containing DTrace program to track CPU idle state transitions
52 ":::idle-state-transition"
55 " self->start = timestamp;"
56 " self->state = arg0;"
59 ":::idle-state-transition"
60 "/arg0 == 0 && self->start/"
62 " @number[self->state] = count();"
63 " @times[self->state] = sum(timestamp - self->start);"
64 " self->start = 0;"
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| /illumos-gate/usr/src/man/man8/ |
| H A D | powertop.8 | 8 powertop \- report and analyze events that affect power management
12 \fBpowertop\fR [\fB-c\fR \fIprocessor_id\fR] [\fB-d\fR \fIcount\fR] [\fB-t\fR \fIinterval\fR] [\fB-…
18 is taking advantage of the CPU's power management features. By running the tool
19 on an otherwise idle system, the user can see for how long the CPU is running
20 at different power states. Ideally, an unutilized (idle) system spends 100%
22 and kernel activity (random software periodically waking to poll status), idle
28 the top activities responsible for causing the CPU to wake up and use more
33 \fBPowerTOP\fR averages the amount of activity that is preventing the CPU from
34 entering a lower power state and presents it on the "Wakeups-from-idle per
35 second" field. This value represents the total number of wake-ups divided by
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| /titanic_41/usr/src/uts/i86pc/io/ |
| H A D | hpet_acpi.c | 79 * hpet_state_lock is used to synchronize disabling/enabling deep c-states
97 * hpet_proxy_users is a per-cpu array.
99 static hpet_proxy_t *hpet_proxy_users; /* one per CPU */
211 * the first available non-legacy replacement timer: timer 2. in hpet_acpi_init()
238 * if it is used for more than just Deep C-State support. in hpet_acpi_init()
240 * value before starting it for use to wake up CPUs from Deep C-States. in hpet_acpi_init()
283 * Do initial setup to use a HPET timer as a proxy for Deep C-state stalled
297 if (hpet_get_IOAPIC_intr_capable_timer(&hpet_info) == -1) { in hpet_init_proxy()
310 hpet_flags->intr_el = INTR_EL_LEVEL; in hpet_init_proxy()
311 hpet_flags->intr_po = INTR_PO_ACTIVE_HIGH; in hpet_init_proxy()
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| /illumos-gate/usr/src/uts/i86pc/io/ |
| H A D | hpet_acpi.c | 84 * hpet_state_lock is used to synchronize disabling/enabling deep c-states
102 * hpet_proxy_users is a per-cpu array.
104 static hpet_proxy_t *hpet_proxy_users; /* one per CPU */
169 * ACPI, programming the interrupt on the non-legacy timer can in hpet_early_init()
191 if (BOP_GETPROPLEN(bootops, "hpet-table") != 8 || in hpet_early_init()
192 BOP_GETPROP(bootops, "hpet-table", (void *)&hpet_table) != 0) { in hpet_early_init()
253 * the first available non-legacy replacement timer: timer 2. in hpet_early_init()
284 * if it is used for more than just Deep C-State support. in hpet_early_init()
286 * value before starting it for use to wake up CPUs from Deep C-States. in hpet_early_init()
358 * If Deep C-States are disabled or not supported, then we do in hpet_acpi_init()
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| /titanic_41/usr/src/man/man1m/ |
| H A D | powertop.1m | 8 powertop \- report and analyze events that affect power management
12 \fBpowertop\fR [\fB-c\fR \fIprocessor_id\fR] [\fB-d\fR \fIcount\fR] [\fB-t\fR \fIinterval\fR] [\fB-…
19 is taking advantage of the CPU's power management features. By running the tool
20 on an otherwise idle system, the user can see for how long the CPU is running
21 at dif- ferent power states. Ideally, an unutilized (idle) system spends 100%
23 and kernel activity (random software periodically waking to poll status), idle
29 the top activities responsible for causing the CPU to wake up and use more
34 \fBPowerTOP\fR averages the amount of activity that is preventing the CPU from
35 entering a lower power state and presents it on the "Wakeups-from-idle per
36 second" field. This value represents the total number of wake-ups divided by
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| /illumos-gate/usr/src/uts/i86pc/sys/ |
| H A D | cpupm_mach.h | 44 * CPU power domains
60 * CPU power management (i.e., Intel has Enhanced SpeedStep for some of its
66 * the current CPU device, then the cpus_init() module should return
81 * Data kept for each C-state power-domain.
84 uint32_t cs_next_cstate; /* computed best C-state */
87 uint32_t cs_type; /* current ACPI idle type */
89 hrtime_t cs_idle_enter; /* entered idle */
90 hrtime_t cs_idle_exit; /* left idle */
93 hrtime_t cs_idle; /* time idle */
95 hrtime_t cs_smpl_idle; /* idle time in last sample */
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| /titanic_41/usr/src/uts/i86pc/sys/ |
| H A D | cpupm_mach.h | 44 * CPU power domains
60 * CPU power management (i.e., Intel has Enhanced SpeedStep for some of its
66 * the current CPU device, then the cpus_init() module should return
81 * Data kept for each C-state power-domain.
84 uint32_t cs_next_cstate; /* computed best C-state */
87 uint32_t cs_type; /* current ACPI idle type */
89 hrtime_t cs_idle_enter; /* entered idle */
90 hrtime_t cs_idle_exit; /* left idle */
93 hrtime_t cs_idle; /* time idle */
95 hrtime_t cs_smpl_idle; /* idle time in last sample */
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| /illumos-gate/usr/src/uts/intel/sys/ |
| H A D | cpu.h | 46 #include <asm/cpu.h>
64 * Used to insert cpu-dependent instructions into spin loops
70 * C-state defines for the idle_state_transition DTrace probe
72 * The probe fires when the CPU undergoes an idle state change (e.g. C-state)
73 * The argument passed is the C-state to which the CPU is transitioning.
75 * These states will be shared by cpupm subsystem, so they should be kept in
76 * consistence with ACPI defined C states.
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| /titanic_41/usr/src/uts/intel/sys/ |
| H A D | cpu.h | 46 #include <asm/cpu.h>
64 * Used to insert cpu-dependent instructions into spin loops
70 * C-state defines for the idle_state_transition DTrace probe
72 * The probe fires when the CPU undergoes an idle state change (e.g. C-state)
73 * The argument passed is the C-state to which the CPU is transitioning.
75 * These states will be shared by cpupm subsystem, so they should be kept in
76 * consistence with ACPI defined C states.
|