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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dscu.txt1 * ARM Snoop Control Unit (SCU)
3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
16 - compatible : Should be:
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
19 "arm,arm11mp-scu"
21 - reg : Specify the base address and the size of the SCU register window.
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H A Darm,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Snoop Control Unit (SCU)
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca9.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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H A Darm-realview-pbx-a9.dts23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
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H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
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/freebsd/sys/contrib/device-tree/Bindings/arm/ux500/
H A Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
22 scu:
23 see binding for arm/arm,scu.yaml
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
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/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm63138.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cell
95 scu: scu@1e000 { global() label
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H A Dbcm-ns.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm/actions/
H A Dowl-s500.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/arm/cpu-enable-method/
H A Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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H A Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2q.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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H A Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
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H A Dberlin2.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,berlin-smp";
34 next-level-cache = <&l2>;
38 clock-latency = <100000>;
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-375.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
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H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
32 compatible = "arm,cortex-a9-pmu";
33 interrupts-extended = <&mpic 3>;
37 compatible = "marvell,armada380-mbus", "simple-bus";
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/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mod
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam4372.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controlle
126 scu: scu@48240000 { global() label
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-reset
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cell
789 scu: snoop-control-unit@ffffc000 { global() label
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H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
812 scu: snoop-control-unit@fffec000 { global() label
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