Home
last modified time | relevance | path

Searched full:coreclock (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c118 u32 coreClock, in ProgramClock() argument
130 coreClock *= 100; /* in Hz */ in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
137 ulMaxClock = coreClock + (coreClock >> 8); in ProgramClock()
140 ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER; in ProgramClock()
179 ((coreClock > STG4K3_PLL_MAXR_VCO) in ProgramClock()
H A DSTG4000Interface.h37 extern u32 ProgramClock(u32 refClock, u32 coreClock, u32 *FOut, u32 *ROut, u32 *POut);
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt47 <&coreclock>, <&coreclock>,
48 <&coreclock>, <&coreclock>;
H A Dcdns,csi2rx.yaml140 <&coreclock 8>, <&coreclock 9>,
141 <&coreclock 10>, <&coreclock 11>;
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c421 enum sparx5_core_clockfreq freq = sparx5->coreclock; in sparx5_init_coreclock()
430 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
432 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
438 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
440 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) in sparx5_init_coreclock()
445 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
447 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) in sparx5_init_coreclock()
451 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
457 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
459 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
[all …]
H A Dsparx5_ptp.c37 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
59 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
H A Dsparx5_calendar.c170 max_core_bw = sparx5_clk_to_bandwidth(sparx5->coreclock); in sparx5_config_auto_calendar()
289 clk_period_ps = sparx5_clk_period(sparx5->coreclock); in sparx5_dsm_calendar_calc()
H A Dsparx5_main.h239 enum sparx5_core_clockfreq coreclock; member
H A Dsparx5_port.c460 u32 sys_clk = sparx5_clk_period(sparx5->coreclock); in sparx5_port_fifo_sz()
/linux/Documentation/devicetree/bindings/i3c/
H A Dcdns,i3c-master.yaml46 clocks = <&coreclock>, <&i3csysclock>;
H A Di3c.yaml161 clocks = <&coreclock>, <&i3csysclock>;
/linux/drivers/phy/microchip/
H A Dsparx5_serdes.h33 unsigned long coreclock; member
H A Dsparx5_serdes.c2187 u32 freq = priv->coreclock == 250000000 ? 2 : in sparx5_serdes_clock_config()
2188 priv->coreclock == 500000000 ? 1 : 0; in sparx5_serdes_clock_config()
2558 /* Get coreclock */ in sparx5_serdes_probe()
2561 dev_err(priv->dev, "Failed to get coreclock\n"); in sparx5_serdes_probe()
2566 dev_err(priv->dev, "Invalid coreclock %lu\n", clock); in sparx5_serdes_probe()
2569 priv->coreclock = clock; in sparx5_serdes_probe()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhardwaremanager.c402 pclock_info->min_eng_clk = performance_level.coreClock; in phm_get_clock_info()
412 pclock_info->max_eng_clk = performance_level.coreClock; in phm_get_clock_info()
H A Dsmu10_hwmgr.c1123 level->coreClock = data->gfx_min_freq_limit; in smu10_get_performance_level()
1127 level->coreClock = data->gfx_max_freq_limit; in smu10_get_performance_level()
H A Dsmu8_hwmgr.c1623 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1628 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
H A Dsmu7_hwmgr.c5725 level->coreClock = ps->performance_levels[i].engine_clock; in smu7_get_performance_level()
/linux/arch/mips/kernel/
H A Didle.c83 * since coreclock (and the cp0 counter) stops upon executing it. Only an
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h271 uint32_t coreClock; member