| H A D | dcn31_fpu.c | 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 454 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) in dcn31_update_soc_for_wm_a() argument 458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a() 459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_tabl in dcn31_update_soc_for_wm_a() 465 dcn315_update_soc_for_wm_a(struct dc * dc,struct dc_state * context) dcn315_update_soc_for_wm_a() argument 483 dcn31_calculate_wm_and_dlg_fp(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel) dcn31_calculate_wm_and_dlg_fp() argument [all...] |