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Searched full:conf_reg (Results 1 – 25 of 31) sorted by relevance

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/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c301 if (pin_reg->conf_reg == -1) { in imx_pinconf_get_mmio()
307 *config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_get_mmio()
336 if (pin_reg->conf_reg == -1) { in imx_pinconf_set_mmio()
348 reg = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
351 writel(reg, ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
353 pin_reg->conf_reg, reg); in imx_pinconf_set_mmio()
355 writel(configs[i], ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
357 pin_reg->conf_reg, configs[i]); in imx_pinconf_set_mmio()
398 if (pin_reg->conf_reg == -1) { in imx_pinconf_dbg_show()
403 config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_dbg_show()
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H A Dpinctrl-imx.h62 * @conf_reg: config register offset
66 s16 conf_reg; member
H A Dpinctrl-imx-scmi.c67 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local
113 conf_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()
132 if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL)) in pinctrl_scmi_imx_dt_node_to_map()
/linux/Documentation/devicetree/bindings/firmware/
H A Dnxp,imx95-scmi-pinctrl.yaml29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
40 "conf_reg" indicates the offset of pad configuration register.
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
47 "conf_reg" indicates the offset of pad configuration register.
H A Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
47 "conf_reg" indicates the offset of pad configuration register.
H A Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "conf_reg" indicates the offset of pad configuration register.
H A Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
55 "conf_reg" indicates the offset of pad configuration register.
H A Dfsl,imx-pinctrl.txt26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/linux/drivers/watchdog/
H A Dbd96801_wdt.c237 unsigned int conf_reg) in bd96801_set_heartbeat_from_hw() argument
247 if ((conf_reg & BD96801_WD_EN_MASK) != BD96801_WD_IF_EN) { in bd96801_set_heartbeat_from_hw()
262 if ((conf_reg & BD96801_WD_TYPE_MASK) == BD96801_WD_TYPE_WIN) in bd96801_set_heartbeat_from_hw()
/linux/drivers/crypto/rockchip/
H A Drk3288_crypto_skcipher.c258 u32 block, conf_reg = 0; in rk_cipher_hw_init() local
268 conf_reg = RK_CRYPTO_DESSEL; in rk_cipher_hw_init()
281 conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | in rk_cipher_hw_init()
283 CRYPTO_WRITE(dev, RK_CRYPTO_CONF, conf_reg); in rk_cipher_hw_init()
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc-snvs.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ull-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx25-pinfunc.h13 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx51-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ul-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimxrt1050-pinfunc.h14 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx50-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6sll-pinfunc.h13 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx35-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6sl-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx93-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx8mn-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx95-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>

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