| /freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
| H A D | xlnx,v-tc.txt | 2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
28 compatible = "xlnx,v-tc-6.1";
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| /freebsd/sys/contrib/device-tree/Bindings/ptp/ |
| H A D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock
5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
9 - reg Offset and length of the register set for the device
10 - interrupts There should be at least two interrupts. Some devices
13 Clock Properties:
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
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| H A D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | silabs,si5351.txt | 1 Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
5 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
7 The Si5351a/b/c are programmable i2c clock generators with up to 8 output
8 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
9 3 output clocks are accessible. The internal structure of the clock
15 - compatible: shall be one of the following:
16 "silabs,si5351a" - Si5351a, QFN20 package
17 "silabs,si5351a-msop" - Si5351a, MSOP10 package
18 "silabs,si5351b" - Si5351b, QFN20 package
19 "silabs,si5351c" - Si5351c, QFN20 package
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| H A D | silabs,si514.txt | 1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
|
| H A D | armada3700-tbg-clock.txt | 1 * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
6 The TBG clock consumer should specify the desired clock by having the
7 clock ID in its "clocks" phandle cell.
9 The following is a list of provided IDs and clock names on Armada 3700:
16 - compatible : shall be "marvell,armada-3700-tbg-clock"
17 - reg : must be the register address of North Bridge PLL register
18 - #clock-cells : from common clock binding; shall be set to 1
23 compatible = "marvell,armada-3700-tbg-clock";
26 #clock-cells = <1>;
|
| H A D | tango4-clock.txt | 1 * Sigma Designs Tango4 Clock Generator
3 The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
4 for RAM and various peripheral devices). The clock binding described here
9 - compatible: should be "sigma,tango4-clkgen".
10 - reg: physical base address of the device and length of memory mapped region.
11 - clocks: phandle of the input clock (crystal oscillator).
12 - clock-output-names: should be "cpuclk" and "sysclk".
13 - #clock-cells: should be set to 1.
18 compatible = "sigma,tango4-clkgen";
21 clock-output-names = "cpuclk", "sysclk";
[all …]
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| H A D | adi,axi-clkgen.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
14 The axi_clkgen IP core is a software programmable clock generator,
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
[all …]
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| H A D | idt,versaclock5.txt | 1 Binding for IDT VersaClock 5,6 programmable i2c clock generators.
3 The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
9 - compatible: shall be one of
16 - reg: i2c device address, shall be 0x68 or 0x6a.
17 - #clock-cells: from common clock binding; shall be set to 1.
18 - clocks: from common clock binding; list of parent clock handles,
19 - 5p49v5923 and
22 reference clock.
23 - 5p49v5933 and
24 - 5p49v5935: (optional) property not present (internal
[all …]
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| H A D | renesas,cpg-mstp-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
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| H A D | renesas,rzv2h-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14 and control of clock signals for the IP modules, generation and control of resets,
19 const: renesas,r9a09g057-cpg
26 - description: AUDIO_EXTAL clock input
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| H A D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15 similar, but does not have Clock Monitor Registers.
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
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| H A D | renesas,cpg-mssr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator / Module Standby and Software Reset
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
20 1. Module Standby, providing a Clock Domain to control the clock supply
[all …]
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| H A D | renesas,cpg-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
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| H A D | idt,versaclock5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
11 clock generators providing from 3 to 12 output clocks.
13 When referencing the provided clock in the DT using phandle and clock
16 - 5P49V5923:
17 0 -- OUT0_SEL_I2CB
18 1 -- OUT1
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| H A D | silabs,si5341.txt | 2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
[all …]
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| H A D | axi-clkgen.txt | 1 Binding for the axi-clkgen clock generator
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
9 - #clock-cells : from common clock binding; Should always be set to 0.
10 - reg : Address and length of the axi-clkgen register set.
11 - clocks : Phandle and clock specifier for the parent clock(s). This must
12 either reference one clock if only the first clock input is connected or two
13 if both clock inputs are connected. For the later case the clock connected
17 - clock-output-names : From common clock binding.
[all …]
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| H A D | silabs,si544.txt | 1 Binding for Silicon Labs 544 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
12 - compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
14 - reg: I2C device address.
15 - #clock-cells: From common clock bindings: Shall be 0.
18 - clock-output-names: From common clock bindings. Recommended to be "si544".
21 si544: clock-controller@55 {
23 #clock-cells = <0>;
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | st,stm32-sai.txt | 4 as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
5 The SAI contains two independent audio sub-blocks. Each sub-block has
6 its own clock generator and I/O lines controller.
9 - compatible: Should be "st,stm32f4-sai" or "st,stm32h7-sai"
10 - reg: Base address and size of SAI common register set.
11 - clocks: Must contain phandle and clock specifier pairs for each entry
12 in clock-names.
13 - clock-names: Must contain "pclk" "x8k" and "x11k"
14 "pclk": Clock which feeds the peripheral bus interface.
15 Mandatory for "st,stm32h7-sai" compatible.
[all …]
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| H A D | st,stm32-sai.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/st,stm32-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Olivier Moysan <olivier.moysan@foss.st.com>
14 protocols as I2S standards, LSB or MSB-justified, PCM/DSP, TDM, and AC'97.
15 The SAI contains two independent audio sub-blocks. Each sub-block has
16 its own clock generator and I/O lines controller.
21 - st,stm32f4-sai
22 - st,stm32h7-sai
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,k3-am654-cpts.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
17 - selection of multiple external clock sources
18 - Software control of time sync events via interrupt or polling
19 - 64-bit timestamp mode in ns with PPM and nudge adjustment.
20 - hardware timestamp push inputs (HWx_TS_PUSH)
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/rng/ |
| H A D | microchip,pic32-rng.txt | 1 * Microchip PIC32 Random Number Generator
3 The PIC32 RNG provides a pseudo random number generator which can be seeded by
4 another true random number generator.
7 - compatible : should be "microchip,pic32mzda-rng"
8 - reg : Specifies base physical address and size of the registers.
9 - clocks: clock phandle.
14 compatible = "microchip,pic32mzda-rng";
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| H A D | samsung,exynos5250-trng.txt | 1 Exynos True Random Number Generator
5 - compatible : Should be "samsung,exynos5250-trng".
6 - reg : Specifies base physical address and size of the registers map.
7 - clocks : Phandle to clock-controller plus clock-specifier pair.
8 - clock-names : "secss" as a clock name.
13 compatible = "samsung,exynos5250-trng";
15 clocks = <&clock CLK_SSS>;
16 clock-names = "secss";
|
| /freebsd/sys/contrib/device-tree/Bindings/crypto/ |
| H A D | samsung-sss.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/crypto/samsung-sss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 -- Feeder (FeedCtrl)
15 -- Advanced Encryption Standard (AES)
16 -- Data Encryption Standard (DES)/3DES
17 -- Public Key Accelerator (PKA)
18 -- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | adi,adv7511.txt | 2 ------------------------------------------------
11 - compatible: Should be one of:
18 - reg: I2C slave addresses
27 color depth, color format, clock mode, bit justification and random
32 - adi,input-depth: Number of bits per color component at the input (8, 10 or
34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per
37 pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as
45 - adi,input-justification: The input bit justification ("left", "evenly",
[all …]
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