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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
[all …]
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Datmel,sama5d2-pdmic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/sound/atmel,sama5d2-pdmic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
20 const: atmel,sama5d2-pdmic
30 - description: peripheral clock
31 - description: generated clock
33 clock-names:
35 - const: pclk
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250-snow-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
[all …]
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
19 chassis-type = "laptop";
33 stdout-path = "serial3:115200n8";
36 gpio-keys {
37 compatible = "gpio-keys";
[all …]
H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
[all …]
H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
[all …]
H A Dexynos5250-arndale.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
32 stdout-path = "serial2:115200n8";
35 gpio-keys {
36 compatible = "gpio-keys";
[all …]
H A Ds5pv210-goni.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
13 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/input/input.h>
38 pmic_ap_clk: clock-0 {
39 /* Workaround for missing clock on PMIC */
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
[all …]
H A Dexynos4210-trats.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
[all …]
H A Dexynos4412-midas.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include "exynos4412-ppmu-common.dtsi"
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/clock/maxim,max77686.h>
20 #include "exynos-pinctrl.h"
34 stdout-path = &serial_2;
38 compatible = "samsung,secure-firmware";
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
82 return -ETIMEDOUT; in measure_clock()
[all …]
/linux/drivers/sh/clk/
H A Dcore.c2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dbase.c44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
55 input = max(boostE.min, input); in nvkm_clk_adjust()
56 input = min(boostE.max, input); in nvkm_clk_adjust()
65 input = max(boostS.min, input); in nvkm_clk_adjust()
66 input = min(boostS.max, input); in nvkm_clk_adjust()
76 * C-States
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
86 while (domain && domain->name != nv_clk_src_max) { in nvkm_cstate_valid()
87 if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) { in nvkm_cstate_valid()
[all …]
/linux/drivers/net/can/dev/
H A Dbittiming.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
11 if (bt->sjw) in can_sjw_set_default()
15 bt->sjw = max(1U, min(bt->phase_seg1, bt->phase_seg2 / 2)); in can_sjw_set_default()
21 if (bt->sjw > btc->sjw_max) { in can_sjw_check()
22 NL_SET_ERR_MSG_FMT(extack, "sjw: %u greater than max sjw: %u", in can_sjw_check()
23 bt->sjw, btc->sjw_max); in can_sjw_check()
24 return -EINVAL; in can_sjw_check()
27 if (bt->sjw > bt->phase_seg1) { in can_sjw_check()
[all …]
/linux/include/linux/
H A Dcpufreq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
49 /* in 10^(-9) s = nanoseconds */
54 /* CPUs sharing clock, require sw coordination */
66 unsigned int min; /* in kHz */ member
67 unsigned int max; /* in kHz */ member
70 unsigned int suspend_freq; /* freq to set during suspend */
94 * - Any routine that wants to read from the policy structure will
96 * - Any routine that will write to the policy structure and/or may take away
104 * - fast_switch_possible should be set by the driver if it can
[all …]
/linux/drivers/net/can/rockchip/
H A Drockchip_canfd-timestamp.c1 // SPDX-License-Identifier: GPL-2.0
4 // Marc Kleine-Budde <kernel@pengutronix.de>
24 ns = timecounter_cyc2time(&priv->tc, timestamp); in rkcanfd_skb_set_timestamp()
26 hwtstamps->hwtstamp = ns_to_ktime(ns); in rkcanfd_skb_set_timestamp()
35 timecounter_read(&priv->tc); in rkcanfd_timestamp_work()
37 schedule_delayed_work(&priv->timestamp, priv->work_delay_jiffies); in rkcanfd_timestamp_work()
42 const struct can_bittiming *dbt = &priv->can.fd.data_bittiming; in rkcanfd_timestamp_init()
43 const struct can_bittiming *bt = &priv->can.bittiming; in rkcanfd_timestamp_init()
44 struct cyclecounter *cc = &priv->cc; in rkcanfd_timestamp_init()
49 /* At the standard clock rate of 300Mhz on the rk3658, the 32 in rkcanfd_timestamp_init()
[all …]
/linux/drivers/clk/
H A Dclk-scpi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * System Control and Power Interface (SCPI) Protocol based clock driver
8 #include <linux/clk-provider.h>
32 return clk->scpi_ops->clk_get_val(clk->id); in scpi_clk_recalc_rate()
41 * after the rate is set and we'll know what rate the clock is in scpi_clk_determine_rate()
52 return clk->scpi_ops->clk_set_val(clk->id, rate); in scpi_clk_set_rate()
66 const struct scpi_opp *opp = clk->info->opps; in __scpi_dvfs_round_rate()
68 for (idx = 0; idx < clk->info->count; idx++, opp++) { in __scpi_dvfs_round_rate()
69 ftmp = opp->freq; in __scpi_dvfs_round_rate()
85 int idx = clk->scpi_ops->dvfs_get_idx(clk->id); in scpi_dvfs_recalc_rate()
[all …]
/linux/drivers/watchdog/
H A Drti_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * (c) Copyright 2019-2020 Texas Instruments Inc.
26 /* Max heartbeat is calculated at 32kHz source clock */
68 * @base - base io address of WD device
69 * @freq - source clock frequency of WDT
70 * @wdd - hold watchdog device as is in WDT core
74 unsigned long freq; member
84 ret = pm_runtime_resume_and_get(wdd->parent); in rti_wdt_start()
89 timer_margin = (u64)wdd->timeout * wdt->freq; in rti_wdt_start()
93 writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD); in rti_wdt_start()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8150-microsoft-surface-duo.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
17 compatible = "microsoft,surface-duo", "qcom,sm8150";
18 chassis-type = "handset";
25 stdout-path = "serial0:115200n8";
28 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr";
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
64 #define STG4K3_PLL_MAX_R 33 /* Max */
66 #define STG4K3_PLL_MAX_F 513 /* Max */
67 #define STG4K3_PLL_MIN_OD 0 /* Min output divider (shift) */
68 #define STG4K3_PLL_MAX_OD 2 /* Max */
69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
[all …]
/linux/drivers/cpufreq/
H A Dgx-suspmod.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (C) 2002 Hiroshi Miura <miura@da-cha.org>
10 * software is provided AS-IS with no warranties.
19 * Suspend Modulation works by asserting and de-asserting the SUSP# pin
21 * the CPU enters an idle state. GX1 stops its core clock when SUSP# is
28 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
35 * F_eff = Fgx * ----------------------
43 * on_duration = off_duration * (stock_freq - freq) / freq
45 * off_duration = (freq * DURATION) / stock_freq
46 * on_duration = DURATION - off_duration
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: regulator-pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]

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