| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra-super-gen4.c | 47 "clk_32k", "pll_m_out1" };
49 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
55 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
71 "clk_32k", "pll_c4_out2" };
73 static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
79 static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
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| H A D | clk-tegra-fixed.c | 102 /* clk_32k */ in tegra_fixed_clk_init()
105 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768); in tegra_fixed_clk_init()
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| H A D | clk-tegra-periph.c | 293 "pll_p", "pll_c", "clk_32k", "clk_m"
447 "pll_p", "clk_m", "clk_32k", "pll_e"
454 "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
474 "pll_p", "pll_c", "clk_m", "clk_32k"
479 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
498 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
503 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
773 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
779 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
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| H A D | clk-tegra124.c | 937 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
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| H A D | clk-tegra210.c | 2563 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
|
| /linux/sound/soc/codecs/ |
| H A D | cs42l52.c | 664 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
665 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
666 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
667 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
668 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
675 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
676 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
677 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
678 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
679 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCL
[all...] |
| H A D | cs42l52.h | 90 #define CLK_32K 0x01 macro
|
| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3506.c | 115 PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" };
117 PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai…
118 PNAME(clk_timer1_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai…
119 PNAME(clk_timer2_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai…
120 PNAME(clk_timer3_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai…
121 PNAME(clk_timer4_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mcl…
122 PNAME(clk_timer5_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mcl…
372 GATE(CLK_USBOTG0_ADP, "clk_usbotg0_adp", "clk_32k", 0,
378 GATE(CLK_USBOTG1_ADP, "clk_usbotg1_adp", "clk_32k", 0,
748 COMPOSITE_NODIV(CLK_32K, "clk_32k", clk_32k_parents_p, CLK_IS_CRITICAL,
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| H A D | clk-rv1126b.c | 139 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
142 "clk_32k" };
180 MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
748 GATE(CLK_PMU_32K_HP_TIMER, "clk_pmu_32k_hp_timer", "clk_32k", CLK_IS_CRITICAL,
757 GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_32k", 0,
782 GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
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| H A D | clk-rk3528.c | 119 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
145 "xin24m", "clk_32k" };
568 /* clk_32k: internal! No path from external osc 32k */
569 MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
571 GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
871 GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
|
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | amlogic,meson8-clkc.yaml | 31 - const: clk_32k
|
| /linux/include/dt-bindings/clock/ |
| H A D | rockchip,rk3506-cru.h | 274 #define CLK_32K 261 macro
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| H A D | rockchip,rv1126b-cru.h | 232 #define CLK_32K 219 macro
|
| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-gru-scarlet.dtsi | 801 &clk_32k /* This pin is always 32k on gru boards */
|
| H A D | rk3399-gru.dtsi | 699 &clk_32k /* This pin is always 32k on gru boards */
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| /linux/drivers/pinctrl/meson/ |
| H A D | pinctrl-meson8b.c | 914 FUNCTION(clk_32k),
|