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/linux/Documentation/devicetree/bindings/power/supply/
H A Dgpio-charger.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/supply/gpio-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
19 const: gpio-charger
21 charger-type:
23 - unknown
24 - battery
25 - ups
[all …]
/linux/drivers/power/supply/
H A Dgpio-charger.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
18 #include <linux/power/gpio-charger.h>
58 struct gpio_mapping mapping; in set_charge_current_limit() local
59 int ndescs = gpio_charger->current_limit_gpios->ndescs; in set_charge_current_limit()
60 struct gpio_desc **gpios = gpio_charger->current_limit_gpios->desc; in set_charge_current_limit()
63 if (!gpio_charger->current_limit_map_size) in set_charge_current_limit()
64 return -EINVAL; in set_charge_current_limit()
66 for (i = 0; i < gpio_charger->current_limit_map_size; i++) { in set_charge_current_limit()
67 if (gpio_charger->current_limit_map[i].limit_ua <= val) in set_charge_current_limit()
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H A Dbq24190_charger.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/extcon-provider.h>
32 #define BQ24190_REG_POC 0x01 /* Power-On Configuration */
56 #define BQ24190_REG_CCC 0x02 /* Charge Current Control */
63 #define BQ24190_REG_PCTCC 0x03 /* Pre-charge/Termination Current Cntl */
75 #define BQ24190_REG_CVC 0x04 /* Charge Voltage Control */
84 #define BQ24190_REG_CTTC 0x05 /* Charge Term/Timer Control */
161 * The tables below provide a 2-way mapping for the value that goes in
162 * the register field and the real-world value that it represents.
164 * number at that index in the array is the real-world value that it
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H A Dbq27xxx_battery.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2010-2011 Lars-Peter Clausen <lars@metafoo.de>
19 * https://www.ti.com/product/bq27510-g1
20 * https://www.ti.com/product/bq27510-g2
21 * https://www.ti.com/product/bq27510-g3
22 * https://www.ti.com/product/bq27520-g1
23 * https://www.ti.com/product/bq27520-g2
24 * https://www.ti.com/product/bq27520-g3
25 * https://www.ti.com/product/bq27520-g4
26 * https://www.ti.com/product/bq27530-g1
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-b1x5pv2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 // Copyright 2018-2021 General Electric Company
7 // Copyright 2018-2021 Collabora
9 #include <dt-bindings/input/input.h>
10 #include "imx6dl-qmx6.dtsi"
14 stdout-path = &uart3;
20 operating-points = <
25 fsl,soc-operating-points = <
26 /* ARM kHz SOC-PU uV */
33 operating-points = <
[all …]
/linux/mm/
H A Dpage-writeback.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mm/page-writeback.c
26 #include <linux/backing-dev.h>
54 #define DIRTY_POLL_THRESH (128 >> (PAGE_SHIFT - 10))
57 * Estimate write bandwidth or update dirty limit at 200ms intervals.
100 * The interval between `kupdate'-style writebacks
119 /* End of sysctl-exporte
499 unsigned long limit = node_dirty_limit(pgdat); node_dirty_ok() local
978 pos_ratio_polynom(unsigned long setpoint,unsigned long dirty,unsigned long limit) pos_ratio_polynom() argument
1073 unsigned long limit = hard_dirty_limit(dtc_dom(dtc), dtc->thresh); wb_position_ratio() local
1301 unsigned long limit = dom->dirty_limit; update_dirty_limit() local
1358 unsigned long limit = hard_dirty_limit(dtc_dom(dtc), dtc->thresh); wb_update_dirty_ratelimit() local
2074 balance_dirty_pages_ratelimited_flags(struct address_space * mapping,unsigned int flags) balance_dirty_pages_ratelimited_flags() argument
2144 balance_dirty_pages_ratelimited(struct address_space * mapping) balance_dirty_pages_ratelimited() argument
2411 tag_pages_for_writeback(struct address_space * mapping,pgoff_t start,pgoff_t end) tag_pages_for_writeback() argument
2433 folio_prepare_writeback(struct address_space * mapping,struct writeback_control * wbc,struct folio * folio) folio_prepare_writeback() argument
2479 writeback_get_folio(struct address_space * mapping,struct writeback_control * wbc) writeback_get_folio() argument
2532 writeback_iter(struct address_space * mapping,struct writeback_control * wbc,struct folio * folio,int * error) writeback_iter() argument
2632 write_cache_pages(struct address_space * mapping,struct writeback_control * wbc,writepage_t writepage,void * data) write_cache_pages() argument
2651 writeback_use_writepage(struct address_space * mapping,struct writeback_control * wbc) writeback_use_writepage() argument
2672 do_writepages(struct address_space * mapping,struct writeback_control * wbc) do_writepages() argument
2716 noop_dirty_folio(struct address_space * mapping,struct folio * folio) noop_dirty_folio() argument
2732 folio_account_dirtied(struct folio * folio,struct address_space * mapping) folio_account_dirtied() argument
2789 __folio_mark_dirty(struct folio * folio,struct address_space * mapping,int warn) __folio_mark_dirty() argument
2823 filemap_dirty_folio(struct address_space * mapping,struct folio * folio) filemap_dirty_folio() argument
2857 struct address_space *mapping = folio->mapping; folio_redirty_for_writepage() local
2893 struct address_space *mapping = folio_mapping(folio); folio_mark_dirty() local
2952 struct address_space *mapping = folio_mapping(folio); __folio_cancel_dirty() local
2989 struct address_space *mapping = folio_mapping(folio); folio_clear_dirty_for_io() local
3074 struct address_space *mapping = folio_mapping(folio); __folio_end_writeback() local
3116 struct address_space *mapping = folio_mapping(folio); __folio_start_writeback() local
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H A Dmemcontrol.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* memcontrol.c - Memory Controller
19 * Charge lifetime sanitation
28 #include <linux/cgroup-defs.h>
39 #include <linux/page-flags.h>
40 #include <linux/backing-de
1296 unsigned long limit; mem_cgroup_margin() local
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H A Dmemcontrol-v1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/backing-dev.h>
17 #include "memcontrol-v1.h"
20 * Cgroups above their limits are maintained in a RB-Tree, independent of
38 * limit reclaim to prevent infinite loops, if they ever occur.
113 struct rb_node **p = &mctz->rb_roo
811 struct address_space *mapping = folio_mapping(folio); mem_cgroup_move_account() local
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_0.h4 * Permission is hereby granted, free of charge, to any person obtaining a
157 // VR Mapping Bit Defines
403 //This is aligned with RSMU PGFSM Register Mapping
409 //This is aligned with RSMU PGFSM Register Mapping
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
944 …oRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
949 …uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperat…
953 …uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to c…
954 …uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to …
[all …]
H A Dsmu13_driver_if_v13_0_7.h4 * Permission is hereby granted, free of charge, to any person obtaining a
158 // VR Mapping Bit Defines
404 //This is aligned with RSMU PGFSM Register Mapping
410 //This is aligned with RSMU PGFSM Register Mapping
504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
953 …oRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
958 …uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperat…
962 …uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to c…
963 …uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to …
[all …]
H A Dsmu14_driver_if_v14_0.h4 * Permission is hereby granted, free of charge, to any person obtaining a
166 // VR Mapping Bit Defines
419 //This is aligned with RSMU PGFSM Register Mapping
425 //This is aligned with RSMU PGFSM Register Mapping
517 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
520 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1042 …oRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
1044 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping
1058 …uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperat…
1090 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping
[all …]
H A Dsmu11_driver_if_arcturus.h4 * Permission is hereby granted, free of charge, to any person obtaining a
44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
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H A Dsmu11_driver_if_navi10.h4 * Permission is hereby granted, free of charge, to any person obtaining a
50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
58 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_svm.c4 * Permission is hereby granted, free of charge, to any person obtaining a
78 #define SVM_DBG(s,f,a...) NV_DEBUG((s)->drm, "svm: "f"\n", ##a)
79 #define SVM_ERR(s,f,a...) NV_WARN((s)->drm, "svm: "f"\n", ##a)
97 list_for_each_entry(ivmm, &svm->inst, head) { in nouveau_ivmm_find()
98 if (ivmm->inst == inst) in nouveau_ivmm_find()
105 NV_DEBUG((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a)
107 NV_WARN((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a)
119 args->va_start &= PAGE_MASK; in nouveau_svmm_bind()
120 args->va_end = ALIGN(args->va_end, PAGE_SIZE); in nouveau_svmm_bind()
123 if (args->reserved0 || args->reserved1) in nouveau_svmm_bind()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_flat_memory.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
58 * System Unified Address - SUA
62 * a combination of vidMM/driver software components. The current virtual
82 * HSA64 - ATC/IOMMU 64b
92 * unified address” feature (SUA) is the mapping of GPUVM and ATC address
114 * A 64b pointer is compared to the apertures that are defined (Base/Limit), in
139 * In all cases (no matter where the 64b -> 49b conversion is done), the gfxip
156 * The default aperture isn’t an actual base/limit aperture; it is just the
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H A Dkfd_events.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
44 bool event_age_enabled; /* set to true when last_event_age is non-zero */
48 * Each signal event needs a 64-bit signal slot where the signaler will write
62 return page->kernel_address; in page_slots()
83 page->kernel_address = backing_store; in allocate_signal_page()
84 page->need_to_free_pages = true; in allocate_signal_page()
101 if (!p->signal_page) { in allocate_event_notification_slot()
102 p->signal_page = allocate_signal_page(p); in allocate_event_notification_slot()
[all …]
/linux/include/drm/
H A Ddrm_gpuvm.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
9 * Permission is hereby granted, free of charge, to any person obtaining a
28 #include <linux/dma-resv.h>
42 * enum drm_gpuva_flags - flags for struct drm_gpuva
55 * Flag indicating that the &drm_gpuva is a sparse mapping.
66 * struct drm_gpuva - structure to track a GPU VA mapping
68 * This structure represents a GPU VA mapping and is associated with a
86 * @flags: the &drm_gpuva_flags for this mapping
126 * @rb: structure containing data to store &drm_gpuvas in a rb-tree
130 * @rb.node: the rb-tree node
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/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_userptr.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2012-2014 Intel Corporation
11 * Permission is hereby granted, free of charge, to any person obtaining a
21 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
50 * i915_gem_userptr_invalidate - callback to notify about mm change
74 return mmu_interval_notifier_insert(&obj->userptr.notifier, current->mm, in i915_gem_userptr_init__mmu_notifier()
75 obj->userptr.ptr, obj->base.size, in i915_gem_userptr_init__mmu_notifier()
85 if (!--obj->userptr.page_ref) { in i915_gem_object_userptr_drop_ref()
86 pvec = obj->userptr.pvec; in i915_gem_object_userptr_drop_ref()
87 obj->userptr.pvec = NULL; in i915_gem_object_userptr_drop_ref()
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/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
72 #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */
75 #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */
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/linux/kernel/
H A Dfork.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * 'fork.c' contains the help-routines for the 'fork' system call
84 #include <linux/posix-timers.h>
85 #include <linux/user-return-notifier.h>
138 static int max_threads; /* tunable limit on nr_threads */
224 if (try_release_thread_stack_to_cache(vm_stack->stack_vm_area)) in thread_stack_free_rcu()
232 struct vm_stack *vm_stack = tsk->stack; in thread_stack_delayed_free()
234 vm_stack->stack_vm_area = tsk->stack_vm_area; in thread_stack_delayed_free()
235 call_rcu(&vm_stack->rcu, thread_stack_free_rcu); in thread_stack_delayed_free()
249 vfree(vm_stack->addr); in free_vm_stack_cache()
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/linux/include/linux/platform_data/
H A Dcros_ec_commands.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
22 * Current version of this protocol
52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
77 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
78 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
79 #define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
81 #define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
82 #define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
83 #define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_uvd.c5 * Permission is hereby granted, free of charge, to any person obtaining a
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
74 switch (rdev->family) { in radeon_uvd_init()
134 return -EINVAL; in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
141 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); in radeon_uvd_init()
143 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", in radeon_uvd_init()
146 struct common_firmware_header *hdr = (void *)rdev->uvd_fw->data; in radeon_uvd_init()
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H A Dradeon_device.c6 * Permission is hereby granted, free of charge, to any person obtaining a
136 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
140 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
144 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
148 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
152 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
161 struct radeon_device *rdev = dev->dev_private; in radeon_is_px()
163 if (rdev->flags & RADEON_IS_PX) in radeon_is_px()
173 while (p && p->chip_device != 0) { in radeon_device_handle_px_quirks()
174 if (rdev->pdev->vendor == p->chip_vendor && in radeon_device_handle_px_quirks()
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/linux/drivers/xen/
H A Dgrant-table.c6 * Copyright (c) 2005-2006, Christopher Clark
7 * Copyright (c) 2004-2005, K A Fraser
15 * Permission is hereby granted, free of charge, to any person obtaining a copy
50 #include <linux/dma-mapping.h>
58 #include <xen/hvc-console.h>
59 #include <xen/swiotlb-xen.h>
64 #include <xen/mem-reservation.h>
121 * Mapping a list of frames for storing grant entries. Frames parameter
176 /* This can be used as an l-value */
188 ((rc = gnttab_expand(count - gnttab_free_count)) < 0)) { in get_free_entries()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gpuvm.c1 // SPDX-License-Identifier: MIT
3 * Copyright 2014-2018 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
23 #include <linux/dma-buf.h>
55 /* Impose limit on how much memory KFD can use */
73 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
82 list_for_each_entry(entry, &mem->attachments, list) in kfd_mem_is_attached()
83 if (entry->bo_va->base.vm == avm) in kfd_mem_is_attached()
90 * reuse_dmamap() - Check whether adev can share the original
93 * If both adev and bo_adev are in direct mapping or
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