| /freebsd/crypto/krb5/src/lib/crypto/builtin/enc_provider/ |
| H A D | aes.c | 1 /* -*- mode: c; c-basic-offset: 4; indent-tabs-mode: nil -*- */
33 * Private per-key data to cache after first generation. We don't
44 #define CACHE(X) ((struct aes_key_info_cache *)((X)->cache)) macro
48 /* Use AES-NI instructions (via assembly functions) when possible. */
82 return CACHE(key)->aesni; in aesni_supported()
88 struct aes_key_info_cache *cache = CACHE(key); in aesni_expand_enc_key() local
90 if (key->keyblock.length == 16) in aesni_expand_enc_key()
91 k5_iEncExpandKey128(key->keyblock.contents, cache->enc_ctx.ks); in aesni_expand_enc_key()
93 k5_iEncExpandKey256(key->keyblock.contents, cache->enc_ctx.ks); in aesni_expand_enc_key()
94 cache->enc_ctx.inf.l = 1; in aesni_expand_enc_key()
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| H A D | camellia.c | 1 /* -*- mode: c; c-basic-offset: 4; indent-tabs-mode: nil -*- */
2 /* lib/crypto/builtin/enc_provider/camellia.c - Camellia enc provider */
33 * Private per-key data to cache after first generation. We don't want to mess
41 #define CACHE(X) ((struct camellia_key_info_cache *)((X)->cache)) macro
56 if (key->cache != NULL) in init_key_cache()
58 key->cache = malloc(sizeof(struct camellia_key_info_cache)); in init_key_cache()
59 if (key->cache == NULL) in init_key_cache()
61 CACHE(key)->enc_ctx.keybitlen = CACHE(key)->dec_ctx.keybitlen = 0; in init_key_cache()
68 if (CACHE(key)->enc_ctx.keybitlen) in expand_enc_key()
70 if (camellia_enc_key(key->keyblock.contents, key->keyblock.length, in expand_enc_key()
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| /freebsd/contrib/processor-trace/libipt/internal/include/ |
| H A D | pt_block_cache.h | 2 * Copyright (c) 2016-2019, Intel Corporation
32 #include "intel-pt.h"
37 /* A block cache entry qualifier.
39 * This describes what to do at the decision point determined by a block cache
64 * This requires a return-address stack update and an indirect branch
78 * query to determine the compression state and either a return-address
98 * - near direct calls that need to maintain the return-address stack.
100 * - near direct jumps that are too far away to be handled with a
101 * block cache entry as they would overflow the displacement field.
106 /* A block cache entry.
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| /freebsd/sbin/dump/ |
| H A D | cache.c | 2 * CACHE.C
4 * Block cache for dump
35 typedef struct Block { struct
36 struct Block *b_HNext; /* must be first field */ argument
39 } Block; typedef
45 static Block **BlockHash;
55 Block *base; in cinit()
57 if ((BlockSize = sblock->fs_bsize * BLKFACTOR) > MAXBSIZE) in cinit()
62 msg("Cache %d MB, blocksize = %d\n", in cinit()
65 base = calloc(sizeof(Block), NBlocks); in cinit()
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| /freebsd/sys/contrib/device-tree/src/riscv/sifive/ |
| H A D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cell
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| H A D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c00
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| /freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/ |
| H A D | tsan_dense_alloc.h | 1 //===-- tsan_dense_alloc.h --------------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // A DenseSlabAlloc is a freelist-based allocator of fixed-size objects.
12 // DenseSlabAllocCache is a thread-local cache for DenseSlabAlloc.
17 //===----------------------------------------------------------------------===//
30 IndexT cache[kSize]; variable
38 typedef DenseSlabAllocCache Cache; typedef
39 typedef typename Cache::IndexT IndexT;
41 static_assert((kL1Size & (kL1Size - 1)) == 0,
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| H A D | sifive-l2-cache.txt | 1 SiFive L2 Cache Controller
2 --------------------------
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
5 acts as directory-based coherency manager.
9 --------------------
10 - compatible: Should be "sifive,fu540-c000-ccache" and "cache"
12 - cache-block-size: Specifies the block size in bytes of the cache.
15 - cache-level: Should be set to 2 for a level 2 cache
17 - cache-sets: Specifies the number of associativity sets of the cache.
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| H A D | sifive-l2-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Level 2 Cache Controller is used to provide access to fast copies
16 of memory for masters in a Core Complex. The Level 2 Cache Controller also
17 acts as directory-based coherency manager.
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| H A D | sifive,ccache0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Composable Cache Controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 The SiFive Composable Cache Controller is used to provide access to fast copies
15 of memory for masters in a Core Complex. The Composable Cache Controller also
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | MemoryDependenceAnalysis.cpp | 1 //===- MemoryDependenceAnalysis.cpp - Mem Deps Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
59 STATISTIC(NumCacheNonLocal, "Number of fully cached non-local responses");
60 STATISTIC(NumCacheDirtyNonLocal, "Number of dirty cached non-local responses");
61 STATISTIC(NumUncacheNonLocal, "Number of uncached non-local responses");
64 "Number of fully cached non-local ptr responses");
66 "Number of cached, but dirty, non-local ptr responses");
67 STATISTIC(NumUncacheNonLocalPtr, "Number of uncached non-local ptr responses");
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| /freebsd/sys/contrib/device-tree/src/riscv/microchip/ |
| H A D | microchip-mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
6 #include "microchip-mpfs-fabric.dtsi"
9 #address-cells = <2>;
10 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
21 i-cache-block-size = <64>;
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|
| H A D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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| /freebsd/sys/contrib/openzfs/man/man8/ |
| H A D | zdb.8 | 1 .\" SPDX-License-Identifier: CDDL-1.0
29 .Op Fl I Ar inflight-I/O-ops
32 .Op Fl U Ar cache
35 .Op Ar poolname Ns Op / Ns Ar dataset Ns | Ns Ar objset-ID
40 .Op Fl U Ar cache
42 .Ar poolname Ns Op Ar / Ns Ar dataset Ns | Ns Ar objset-ID
47 .Op Fl U Ar cache
49 .Ar poolname Ns Ar / Ns Ar objset-ID
50 .Op Ar backup-flags
54 .Op Fl U Ar cache
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| /freebsd/contrib/libyaml/src/ |
| H A D | scanner.c | 18 * is a straightforward implementation of a recursive-descendant parser (or,
22 * rest is quite straightforward. The issues are "block collection start" and
30 * STREAM-START(encoding) # The stream start.
31 * STREAM-END # The stream end.
32 * VERSION-DIRECTIVE(major,minor) # The '%YAML' directive.
33 * TAG-DIRECTIVE(handle,prefix) # The '%TAG' directive.
34 * DOCUMENT-START # '---'
35 * DOCUMENT-END # '...'
36 * BLOCK-SEQUENCE-START # Indentation increase denoting a block
37 * BLOCK-MAPPING-START # sequence or a block mapping.
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | InterferenceCache.h | 1 //===- InterferenceCache.h - Caching per-block interference ----*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // InterferenceCache remembers per-block interference from LiveIntervalUnions,
12 //===----------------------------------------------------------------------===//
33 /// BlockInterference - information about the interference in a single basic
34 /// block.
43 /// Entry - A cache entry containing interference information for all aliases
46 /// PhysReg - The register currently represented.
49 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | sifive,ccache0.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
6 $schema: http://devicetree.org/meta-schema
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| H A D | starfive,jh8100-starlink-cache.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cache/starfive,jh8100-starlink-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive StarLink Cache Controller
10 - Joshua Yeong <joshua.yeong@starfivetech.com>
13 StarFive's StarLink Cache Controller manages the L3 cache shared between
14 clusters of CPU cores. The cache driver enables RISC-V non-standard cache
15 management as an alternative to instructions in the RISC-V Zicbom extension.
18 - $ref: /schemas/cache-controller.yaml#
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/ |
| H A D | SectionMemoryManager.h | 1 //===- SectionMemoryManager.h - Memory manager for MCJIT/RtDyld -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the declaration of a section-based memory manager used by
12 //===----------------------------------------------------------------------===//
27 /// the RuntimeDyld class to allocate memory for section-based loading of
30 /// This memory manager allocates all section memory as read-write. The
34 /// Any client using this memory manager MUST ensure that section-specific
55 /// case an attempt is made to allocate more memory near the existing block.
58 /// block of the memory. \p EC [out] returns an object describing any error
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| /freebsd/sys/contrib/device-tree/src/riscv/thead/ |
| H A D | th1520.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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| /freebsd/stand/common/ |
| H A D | bcache.c | 1 /*-
30 * Simple hashed block cache
56 * bcache per device node. cache is allocated on device first open and freed
74 static u_int bcache_units; /* number of devices with cache */
83 #define BHASH(bc, blkno) ((blkno) & ((bc)->bcache_nblks - 1))
85 ((bc)->bcache_ctl[BHASH((bc), (blkno))].bc_blkno != (blkno))
95 * Initialise the cache for (nblks) of (bsize).
106 * add number of devices to bcache. we have to divide cache space
135 * the bcache block count must be power of 2 for hash function in bcache_allocate()
137 i = fls(disks) - 1; /* highbit - 1 */ in bcache_allocate()
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| /freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/cache/ |
| H A D | cache_010_pos.ksh | 1 #!/bin/ksh -p
2 # SPDX-License-Identifier: CDDL-1.0
11 # or https://opensource.org/licenses/CDDL-1.0.
33 . $STF_SUITE/tests/functional/cache/cache.cfg
34 . $STF_SUITE/tests/functional/cache/cache.kshlib
38 # Verify that cache devices can be block devices, files or character devices
42 # 2. Add different object as cache
51 if [[ -n $lofidev ]]; then
53 losetup -d $lofidev
55 mdconfig -du ${lofidev#md}
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| /freebsd/sys/riscv/riscv/ |
| H A D | cbo.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
28 /* Cache Block Operations. */
45 va &= ~(dcache_line_size - 1); in cbo_zicbom_cpu_dcache_wbinv_range()
58 * a set of non-coherent agents visible to the set of coherent agents at in cbo_zicbom_cpu_dcache_inv_range()
59 * a point common to both sets by deallocating all copies of a cache in cbo_zicbom_cpu_dcache_inv_range()
60 * block from the set of coherent caches up to that point. in cbo_zicbom_cpu_dcache_inv_range()
63 va &= ~(dcache_line_size - 1); in cbo_zicbom_cpu_dcache_inv_range()
76 * set of coherent agents visible to a set of non-coherent agents at a in cbo_zicbom_cpu_dcache_wb_range()
78 * a cache block to that point provided a coherent agent performed a in cbo_zicbom_cpu_dcache_wb_range()
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| /freebsd/sys/contrib/device-tree/src/riscv/kendryte/ |
| H A D | k210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/k210-clk.h>
10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 #address-cells = <1>;
14 #size-cells = <1>;
23 * Since this is a non-ratified draft specification, the kernel does not
28 #address-cells = <1>;
29 #size-cells = <0>;
30 timebase-frequency = <7800000>;
36 mmu-type = "none";
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