Searched +full:bus +full:- +full:rightbus (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Samsung Exynos SoC Bus and Interconnect10 - Chanwoo Choi <cw00.choi@samsung.com>11 - Krzysztof Kozlowski <krzk@kernel.org>15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.16 Generally, each bus of Exynos SoC includes a source clock and a power line,17 which are able to change the clock frequency of the bus in runtime. To[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.7 * Copyright (c) 2010-2011 Linaro Ltd.20 #include "exynos4-cpu-thermal.dtsi"31 bus_acp: bus-acp {32 compatible = "samsung,exynos-bus";34 clock-names = "bus";35 operating-points-v2 = <&bus_acp_opp_table>;38 bus_acp_opp_table: opp-table {39 compatible = "operating-points-v2";[all …]
1 // SPDX-License-Identifier: GPL-2.019 #include "exynos4-cpu-thermal.dtsi"27 fimc-lite0 = &fimc_lite_0;28 fimc-lite1 = &fimc_lite_1;31 bus_acp: bus-acp {32 compatible = "samsung,exynos-bus";34 clock-names = "bus";35 operating-points-v2 = <&bus_acp_opp_table>;38 bus_acp_opp_table: opp-table {39 compatible = "operating-points-v2";[all …]
1 // SPDX-License-Identifier: GPL-2.017 #include "exynos4-cpu-thermal.dtsi"18 #include <dt-bindings/clock/exynos3250.h>19 #include <dt-bindings/interrupt-controller/arm-gic.h>20 #include <dt-bindings/interrupt-controller/irq.h>24 interrupt-parent = <&gic>;25 #address-cells = <1>;26 #size-cells = <1>;46 bus_dmc: bus-dmc {47 compatible = "samsung,exynos-bus";[all …]