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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dbase.c33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
/linux/include/xen/interface/
H A Dmemory.h27 * OUT: MFN (*not* GMFN) bases of extents that were allocated
29 * IN: GMFN bases of extents to free
31 * IN: GPFN bases of extents to populate with memory
32 * OUT: GMFN bases of extents that were allocated
68 * [IN] Details of memory extents to be exchanged (GMFN bases).
80 * 4. @out.extent_start lists GPFN bases to be populated
81 * 5. @out.extent_start is overwritten with allocated GMFN bases
116 * Returns a list of MFN bases of 2MB extents comprising the machine_to_phys
/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c36 void __iomem *bases[MAX_SMMU_INSTANCES]; member
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
322 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
330 nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
331 if (IS_ERR(nvidia_smmu->bases[i])) in nvidia_smmu_impl_init()
332 return ERR_CAST(nvidia_smmu->bases[i]); in nvidia_smmu_impl_init()
/linux/kernel/time/
H A Dposix-cpu-timers.c28 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
35 * tsk->signal->posix_cputimers.bases[clock].nextevt expiration cache if
154 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
155 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
156 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
422 return tsk->posix_cputimers.bases + clkidx; in timer_base()
424 return tsk->signal->posix_cputimers.bases + clkidx; in timer_base()
626 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
627 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
628 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
[all …]
/linux/arch/x86/boot/
H A Dearly_serial_console.c77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
/linux/drivers/clk/ux500/
H A Dreset-prcc.h13 * @base: the remapped PRCC bases
/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c155 static unsigned int bases[] = { in scaler_set_src_base() local
163 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
218 static unsigned int bases[] = { in scaler_set_dst_base() local
226 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek-hw.yaml25 Addresses and sizes for the memory of the HW bases in
/linux/drivers/sh/intc/
H A Dirqdomain.c59 * tree penalty for linear cases with non-zero hwirq bases. in intc_irq_domain_init()
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt6797.c17 * MT6797 have multiple bases to program pin configuration listed as the below:
/linux/drivers/gpu/host1x/
H A Ddev.h102 unsigned int nb_bases; /* host1x: number of syncpoint bases supported */
138 struct host1x_syncpt_base *bases; member
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcik_regs.h26 /* if PTR32, these are the bases for scratch and lds */
/linux/drivers/staging/media/meson/vdec/
H A Dvdec_helpers.h16 * @reg_base: Registry bases of where to write the canvas indexes
/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfb.h65 void __iomem *host; /* relocatable reg. bases */
/linux/Documentation/timers/
H A Dhighres.rst169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
/linux/drivers/platform/mellanox/
H A DKconfig59 are defined per system type bases and include the registers related
/linux/arch/loongarch/include/asm/
H A Dhw_breakpoint.h44 /* Virtual debug register bases. */
/linux/arch/arm/mach-lpc32xx/
H A Dlpc32xx.h93 * Internal memory bases and sizes
99 * External Static Memory Bank Address Space Bases
107 * External SDRAM Memory Bank Address Space Bases
/linux/drivers/gpu/drm/msm/
H A DNOTES58 register interface is same, just different bases.)
/linux/arch/arm64/include/asm/
H A Dhw_breakpoint.h85 /* Virtual debug register bases. */
/linux/drivers/comedi/drivers/
H A D8255.c32 * option list should be a list of the I/O port bases for each of the
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-tsens.yaml130 bases and two cells per each sensor
135 bases and two cells per each sensor, main and backup copies, plus use_backup cell
/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.c82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
/linux/arch/x86/kernel/
H A Dearly_printk.c171 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; in early_serial_init() local
178 early_serial_base = bases[port]; in early_serial_init()
/linux/arch/m68k/amiga/
H A Dcia.c6 * The concept of some functions bases on the original Amiga OS function

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