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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td222 def f2FFTOS32_S : F2_XZ_P<0b01000, 0b011011, "fftoi.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
223 def f2FFTOU32_S : F2_XZ_P<0b01000, 0b011010, "fftoi.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
226 def f2FFTOXU32_S : F2_XZ_P<0b01000, 0b001010, "fftox.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
227 def f2FFTOXS32_S : F2_XZ_P<0b01000, 0b001011, "fftox.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
231 def f2FFTOS32_D : F2_XZ_P<0b01000, 0b011101, "fftoi.f64.s32", [], (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
232 def f2FFTOU32_D : F2_XZ_P<0b01000, 0b011100, "fftoi.f64.u32", [], (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
235 def f2FFTOXU32_D : F2_XZ_P<0b01000, 0b001100, "fftox.f64.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
236 def f2FFTOXS32_D : F2_XZ_P<0b01000, 0b001101, "fftox.f64.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
243 defm f2FF32TOFI32 : F2_XZ_RM<0b01000, 0b1001, "fftofi.f32", (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
247 defm f2FF64TOFI32 : F2_XZ_RM<0b01000,
[all...]
H A DCSKYInstrInfo.td1040 def DCACHE_IALL32 : I_5_CACHE<0b100101, 0b01000, "dcache32.iall">;
1051 def ICACHE_IALL32 : I_5_CACHE<0b100100, 0b01000, "icache32.iall">;
1064 def L2CACHE_IALL : I_5_CACHE<0b100110, 0b01000, "l2cache.iall">;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td43 def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
47 def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
H A DRISCVInstrInfoZa.td152 defm AMOOR_B : AMO_rr_aq_rl<0b01000, 0b000, "amoor.b">,
171 defm AMOOR_H : AMO_rr_aq_rl<0b01000, 0b001, "amoor.h">,
H A DRISCVInstrInfoXTHead.td392 def TH_LRW : THLoadIndexed<GPR, 0b01000, "th.lrw">,
407 def TH_SRW : THStoreIndexed<GPR, 0b01000, "th.srw">,
450 def TH_FLRW : THLoadIndexed<FPR32, 0b01000, "th.flrw">,
452 def TH_FSRW : THStoreIndexed<FPR32, 0b01000, "th.fsrw">,
721 def TH_DCACHE_CPAL1 : THCacheInst_r<0b01000, "th.dcache.cpal1">;
H A DRISCVInstrInfoZfbfmin.td21 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
H A DRISCVInstrInfoA.td78 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
105 defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">,
H A DRISCVInstrInfoZfa.td133 : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
H A DRISCVInstrInfoXCV.td500 defm SRL : CVSIMDShift<0b01000, 0, 0, "srl">;
558 defm CMPLTU : CVSIMDBinaryUnsigned<0b01000, 1, 0, "cmpltu">;
H A DRISCVInstrInfoZvk.td138 def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMTInstrFormats.td36 def FIELD5_MFTR : FIELD5<0b01000>;
H A DMipsDSPInstrInfo.td137 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
183 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
218 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
230 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
247 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
H A DMips16InstrFormats.td282 let Opcode = 0b01000;
544 let Inst{15-11} = 0b01000;
H A DMips32r6InstrFormats.td140 def FIELD_CMP_COND_SAF : FIELD_CMP_COND<0b01000>;
H A DMicroMips32r6InstrInfo.td228 class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SMEInstrInfo.td211 …defm FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, nxv16i8, "ftmopa", int_aarch64_…
1071 defm FMLALL_MZZ_BtoS : sme2_mla_ll_array_single<"fmlall", 0b01000, MatrixOp32, ZPR8, ZPR4b8, …
1075 defm FMLALL_VG2_M2Z2Z_BtoS : sme2_mla_ll_array_vg2_multi<"fmlall", 0b01000, MatrixOp32, ZZ_b_mul_r,…
1076 defm FMLALL_VG4_M4Z4Z_BtoS : sme2_mla_ll_array_vg4_multi<"fmlall", 0b01000, MatrixOp32, ZZZZ_b_mul_…
H A DAArch64InstrInfo.td5693 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
5694 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
6034 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
6051 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
6401 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
6408 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
6476 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
6477 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
8459 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri", AArch64vsri>;
8537 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", AArch64vsri>;
H A DAArch64SVEInstrInfo.td2255 defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch", int_aarch64_sve_sqinch_n32>;
2282 defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16, int_aarch64_sve_sqinch, nxv8i16>;
2305 defm SQDECP_XPWd : sve_int_count_r_s32<0b01000, "sqdecp", int_aarch64_sve_sqdecp_n32>;
2314 defm SQDECP_ZP : sve_int_count_v<0b01000, "sqdecp", int_aarch64_sve_sqdecp>;
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhi3620.dtsi184 uart1: serial@b01000 {
H A Dhi3620-hi4511.dts37 uart1: serial@b01000 { /* modem */
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td639 let Inst{15-11} = 0b01000;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td1203 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1206 let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi372 rmtfs_mem: memory@89b01000 {
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td409 def OR_3r : F3R<0b01000, "or", or>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp101 // 0b01000: XOP map select - 08h instructions with imm byte

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