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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra SOR Output Encoder
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
19 pattern: "^sor@[0-9a-f]+$"
23 - enum:
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dps8640.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Boichat <drinkcat@chromium.org>
13 The PS8640 is a low power MIPI-to-eDP video format converter supporting
28 powerdown-gpios:
32 reset-gpios:
36 vdd12-supply:
37 description: Regulator for 1.2V digital core power.
39 vdd33-supply:
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Douglas Anderson <dianders@chromium.org>
23 enable-gpios:
27 suspend-gpios:
31 no-hpd:
37 vccio-supply:
40 vpll-supply:
43 vcca-supply:
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,kpss-acc-v1.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
10 - Christian Marangi <ansuelsmth@gmail.com>
13 The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
17 clock-controller for enabling the cpu and handling the aux clocks.
21 const: qcom,kpss-acc-v1
25 - description: Base address and size of the register region
[all …]
/linux/sound/soc/codecs/
H A Dcs42l73.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
26 #include <sound/soc-dapm.h>
54 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
55 { 7, 0xDF }, /* r07 - Power Ctl 2 */
56 { 8, 0x3F }, /* r08 - Power Ctl 3 */
57 { 9, 0x50 }, /* r09 - Charge Pump Freq */
58 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
59 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
60 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
[all …]
H A Dmt6357.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
19 regmap_write(priv->regmap, MT6357_GPIO_MODE2_CLR, MT6357_GPIO_MODE2_CLEAR_ALL); in set_playback_gpio()
22 regmap_write(priv->regmap, MT6357_GPIO_MODE2_SET, in set_playback_gpio()
32 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0, in set_playback_gpio()
46 regmap_write(priv->regmap, MT6357_GPIO_MODE3_CLR, MT6357_GPIO_MODE3_CLEAR_ALL); in set_capture_gpio()
49 regmap_write(priv->regmap, MT6357_GPIO_MODE3_SET, in set_capture_gpio()
58 * will also have 26m, so will have power leak in set_capture_gpio()
61 regmap_update_bits(priv->regmap, MT6357_GPIO_DIR0, in set_capture_gpio()
77 /* Enable/Reduce HPL/R main output stage step by step */ in hp_main_output_ramp()
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H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* -54dB */
35 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
36 /* -52.5dB to 15dB */
37 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
42 /* -78dB to 12dB */
43 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
52 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
53 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
54 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
[all …]
H A Dak4535.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ak4535.c -- AK4535 ALSA Soc Audio driver
65 static const char *ak4535_mono_gain[] = {"+6dB", "-17dB"};
66 static const char *ak4535_mono_out[] = {"(L + R)/2", "Hi-Z"};
81 SOC_ENUM("Mono 1 Output", ak4535_enum[1]),
83 SOC_ENUM("Headphone Output", ak4535_enum[2]),
97 SOC_SINGLE("AUX Bypass Volume", AK4535_VOL, 0, 15, 0),
111 SOC_DAPM_SINGLE("Aux Bypass Switch", AK4535_SIG2, 5, 1, 0),
117 SOC_DAPM_SINGLE("Aux Capture Switch", AK4535_MIC, 5, 1, 0),
180 SND_SOC_DAPM_PGA("AUX In", AK4535_PM1, 2, 0, NULL, 0),
[all …]
/linux/sound/mips/
H A Dad1843.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
35 ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
47 ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
48 ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
49 ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
50 ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
51 ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
52 ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
53 ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
[all …]
/linux/sound/pci/oxygen/
H A Dxonar_dg.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * ------------
18 * SPI 0 -> CS4245
21 * I²S 1 -> CS4245
22 * I²S 2 -> CS4361 (center/LFE)
23 * I²S 3 -> CS4361 (surround)
24 * I²S 4 -> CS4361 (front)
26 * I²S ADC 1 <- CS4245
28 * GPIO 3 <- ?
29 * GPIO 4 <- headphone detect
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
142 * @aux: Our aux channel.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dparade,ps8830.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
15 - items:
16 - const: parade,ps8833
17 - const: parade,ps8830
18 - const: parade,ps8830
25 - description: XO Clock
27 reset-gpios:
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-engicam-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 vcc5v0_sys: regulator-vcc5v0-sys {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc5v0_sys"; /* +5V */
18 regulator-always-on;
19 regulator-boot-on;
20 regulator-min-microvolt = <5000000>;
21 regulator-max-microvolt = <5000000>;
24 sdio_pwrseq: sdio-pwrseq {
25 compatible = "mmc-pwrseq-simple";
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2019-2022 MediaTek Inc.
18 #include <linux/arm-smccc.h>
23 #include <linux/media-bus-format.h>
24 #include <linux/nvmem-consumer.h>
33 #include <sound/hdmi-codec.h>
118 struct drm_dp_aux aux; member
402 .name = "mtk-dp-registers",
415 ret = regmap_read(mtk_dp->regs, offset, &read_val); in mtk_dp_read()
417 dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n", in mtk_dp_read()
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-steelix.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 pp1000_edpbrdg: regulator-pp1000-edpbrdg {
13 compatible = "regulator-fixed";
14 regulator-name = "pp1000_edpbrdg";
15 pinctrl-names = "default";
16 pinctrl-0 = <&en_pp1000_edpbrdg>;
[all …]
H A Dmt8186-corsola-krabby.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
17 remote-endpoint = <&ps8640_in>;
21 clock-frequency = <400000>;
23 edp-bridge@8 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&ps8640_pins>;
28 powerdown-gpios = <&pio 96 GPIO_ACTIVE_LOW>;
[all …]
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h146 * Physical framebuffer address location, 64-bit.
265 * @knee_threshold: Current x-position of ACE knee (u0.16).
285 * union dmub_addr - DMUB physical/virtual 64-bit address.
350 * Back to back flip, therefore cannot power down PHY
391 * @force_phy_power_on: Force phy power on
467 * 0x1 (bit 0) - Desync Error flag.
472 * 0x2 (bit 1) - State Transition Error flag.
477 * 0x4 (bit 2) - Crc Error flag
482 * 0x8 (bit 3) - Reserved
487 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779g3-sparrow-hawk.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H ES3.0 Sparrow Hawk board
17 * for Capture (Aux/Mic)
20 * CONN3 (HeadSet) ---+----> MSIOF1
22 * CONN4 AUX ---------+ on/off (A)
28 * > amixer set "Aux" on ^
29 * > amixer set "Aux" 80% | (A)
30 * > amixer set "Mixin Left Aux Left" on |
31 * > amixer set "Mixin Right Aux Right" on v
36 * > arecord -f cd xxx.wav
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2007-2011, Intel Corporation.
21 #include "power.h"
37 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108)
38 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100)
39 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0)
422 /* Power */
433 /* OSPM info (Power management base) (TODO: can go ?) */
503 * xrandr -- consider removing and using HAL instead
547 int pipes; /* Number of output pipes */
[all …]
/linux/drivers/iio/frequency/
H A Dadf4350.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
22 #include <linux/clk-provider.h>
83 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) { in adf4350_sync_config()
84 if ((st->regs_hw[i] != st->regs[i]) || in adf4350_sync_config()
93 st->val = cpu_to_be32(st->regs[i] | i); in adf4350_sync_config()
94 ret = spi_write(st->spi, &st->val, 4); in adf4350_sync_config()
97 st->regs_hw[i] = st->regs[i]; in adf4350_sync_config()
98 dev_dbg(&st->spi->dev, "[%d] 0x%X\n", in adf4350_sync_config()
99 i, (u32)st->regs[i] | i); in adf4350_sync_config()
[all …]
/linux/include/linux/
H A Dvga_switcheroo.h2 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
39 * enum vga_switcheroo_handler_flags_t - handler flags bitmask
44 * the AUX channel separately. This signals to clients that the active
47 * skip the AUX handshake and set up its output with these pre-calibrated
59 * enum vga_switcheroo_state - client power state
66 * Client power state.
76 * enum vga_switcheroo_client_id - client identifier
94 * struct vga_switcheroo_handler - handler callbacks
102 * Mandatory. For muxless machines this should be a no-op. Returning 0
108 * @power_state: cut or reinstate power of given client.
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
22 - description: AHB clock for PCIe master
23 - description: AHB clock for PCIe slave
24 - description: AHB clock for PCIe dbi
[all …]

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