Searched full:arranged (Results 1 – 25 of 108) sorted by relevance
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17 a bitmap array arranged in 32bit slices where each bit represent signal/line47 HTE lines are arranged in 32 bit slice where each bit represents different
21 struct page arranged in one or more arrays.87 The `mem_section` objects are arranged in a two-dimensional array
17 * The exception fixup information "just so happens" to be arranged
269 * subtracted out. This is arranged so that folks manipulating ISA
19 arranged in vertical stripe.
27 are always arranged in memory from left to right, and from top to
29 The second plane provides 16-bit per-pixel Depth data arranged in
40 slot for this processor has been loaded. We've arranged
19 * Keep this list arranged in rough order of priority. Anything listed after
40 compute tiles arranged into 5 columns. AMD Strix Point client APU have 4x841 topology, i.e., 4 rows of compute tiles arranged into 8 columns.
34 * arranged as shown below:
154 * arranged as shown below:211 * arranged as shown below:248 * Control-bits are arranged as shown below:278 * They are arranged as shown below:
116 /* managed XArray arranged in physical block number */259 /* bitlock definitions (arranged in reverse order) */
74 packets of data arranged back to back. It can be done as follows:
45 /* The fetch and add registers are allocated here. They are arranged
66 * remote node index so the table is arranged in sets of three. The bits are
31 * are arranged for flexibility. We convert the table data to host native
47 and your userspace is arranged correctly, this will be loaded
56 Extents are arranged as a tree. Each node of the tree begins with a
97 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
86 /* Flat array, arranged in groups */
46 /* 16-bit c_can registers can be arranged differently in the memory
87 The number of power domains matches the number of channels, arranged