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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
21 number is defined at design time, the maximum of each defined in the DEVID
25 programmable channels, usually 4, but again implementation defined and
31 are implementation defined, except when the CTI is connected to an ARM v8
36 architecturally connected CTI an additional compatible string is used to
37 indicate this feature (arm,coresight-cti-v8-arch).
51 and usages. These can be defined along with the signal indexes with the
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/linux/arch/arm/include/asm/
H A Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
/linux/Documentation/devicetree/bindings/timer/
H A Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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H A Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - const: arm,cortex-a15-timer
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/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
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/linux/arch/parisc/kernel/
H A Dvmlinux.lds.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
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/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A Dpipeline.json107 …architecturally defined event. This event counts the number of retired branch instructions that we…
116 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
126 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
136 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
146 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
156 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
164 …by dividing the event count by the core frequency. This event is architecturally defined and is a …
189 …lapsed time while the core was not in halt state. This event is architecturally defined and is a …
206 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
215 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
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/linux/Documentation/arch/x86/
H A Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to common_interrupt()
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/linux/arch/x86/lib/
H A Dretpoline.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include <asm/asm-offsets.h>
10 #include <asm/nospec-branch.h>
65 #include <asm/GEN-for-each-reg.h>
72 #include <asm/GEN-for-each-reg.h>
94 #include <asm/GEN-for-each-reg.h>
101 #include <asm/GEN-for-each-reg.h>
120 #include <asm/GEN-for-each-reg.h>
127 #include <asm/GEN-for-each-reg.h>
137 * relocations for same-section JMPs and that breaks the returns
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/linux/arch/x86/mm/
H A Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
32 * NOTE! For PAE, any changes to the top page-directory-pointer-table in ___pmd_free_tlb()
36 tlb->need_flush_all = 1; in ___pmd_free_tlb()
62 list_add(&ptdesc->pt_list, &pgd_list); in pgd_list_add()
69 list_del(&ptdesc->pt_list); in pgd_list_del()
74 virt_to_ptdesc(pgd)->pt_mm = mm; in pgd_set_mm()
79 return page_ptdesc(page)->pt_mm; in pgd_page_get_mm()
103 * List of all pgd's needed for non-PAE so it can invalidate entries
106 * tactic would be needed. This is essentially codepath-based locking
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/linux/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
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H A Dcoresight-etm4x-reference.rst11 ---------------------------
20 ----
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
77 When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for trace session. Otherwise -1
86 ----
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/linux/arch/arm64/kvm/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
81 vcpu->arch.sve_max_vl = kvm_sve_max_vl; in kvm_vcpu_enable_sve()
88 set_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &vcpu->kvm->arch.flags); in kvm_vcpu_enable_sve()
93 * vcpu->arch.sve_state as necessary.
102 vl = vcpu->arch.sve_max_vl; in kvm_vcpu_finalize_sve()
107 * set_sve_vls(). Double-check here just to be sure: in kvm_vcpu_finalize_sve()
111 return -EIO; in kvm_vcpu_finalize_sve()
116 return -ENOMEM; in kvm_vcpu_finalize_sve()
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/linux/drivers/clocksource/
H A Darc_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
75 * defined in arch/arc/kernel/mcip.c in arc_read_gfrc()
110 pr_warn("Global-64-bit-Ctr clocksource not detected\n"); in arc_cs_setup_gfrc()
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/linux/arch/arm64/include/uapi/asm/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
58 * Supported CPU Targets - Adding a new target type is not recommended,
127 * Although the control registers are architecturally defined as 32
150 * Architecture specific defines for kvm_guest_debug->control
161 /* Bits for run->s.regs.device_irq_level */
266 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
275 /* KVM-as-firmware specific pseudo-registers */
287 * - NOT_REQUIRED: the guest doesn't need to do anything
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/linux/tools/arch/arm64/include/uapi/asm/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
58 * Supported CPU Targets - Adding a new target type is not recommended,
127 * Although the control registers are architecturally defined as 32
150 * Architecture specific defines for kvm_guest_debug->control
161 /* Bits for run->s.regs.device_irq_level */
266 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
275 /* KVM-as-firmware specific pseudo-registers */
287 * - NOT_REQUIRED: the guest doesn't need to do anything
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/linux/arch/arm/probes/
H A Ddecode.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* str_pc_offset is architecturally defined from ARMv7 onwards */
32 /* We need a run-time check to determine str_pc_offset */
41 long cpsr = regs->ARM_cpsr; in bx_write_pc()
49 regs->ARM_cpsr = cpsr; in bx_write_pc()
50 regs->ARM_pc = pcv; in bx_write_pc()
62 /* We need run-time testing to determine if load_write_pc() should interwork. */
73 regs->ARM_pc = pcv; in load_write_pc()
90 /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
101 regs->ARM_pc = pcv; in alu_write_pc()
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/linux/include/linux/
H A Dcoresight.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Peripheral id registers (0xFD0-0xFEC) */
26 /* Component id registers (0xFF0-0xFFC) */
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
82 * @link_subtype: type of link this component is, as defined
84 * @source_subtype: type of source this component is, as defined
86 * @helper_subtype: type of helper this component is, as defined
100 * struct coresight_platform_data - data harvested from the firmware
119 * struct csdev_access - Abstraction of a CoreSight device access.
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/linux/arch/arm64/mm/
H A Dfault.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
21 #include <linux/page-flags.h>
37 #include <asm/debug-monitors.h>
110 esr_to_fault_info(esr)->name); in mem_abort_decode()
120 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
122 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
136 mm = current->active_mm; in show_pte()
151 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", in show_pte()
203 * like __set_ptes(), the PTE is never changed from no-exec to exec here.
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/linux/Documentation/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
10 (PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
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/linux/arch/x86/kvm/
H A Dx86.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
59 (sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES)
66 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation.
67 * Spilling over to an order-2 allocation isn't fundamentally problematic, but
69 * the size is an order-0 allocation when ignoring the memslot hash tables, to
74 BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) && \
129 val -= modifier; in __shrink_ple_window()
143 kvm_x86_ops.nested_ops->leave_nested(vcpu); in kvm_leave_nested()
166 return vcpu->arch.last_vmentry_cpu != -1; in kvm_vcpu_has_run()
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/linux/Documentation/arch/arm64/
H A Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
33 ---------------------------
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
96 - code0/code1 are responsible for branching to stext.
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/linux/arch/x86/kernel/cpu/
H A Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/platform_data/x86/amd-fch.h>
18 #include <asm/spec-ctrl.h>
21 #include <asm/pci-direct.h>
75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
101 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ in init_amd_k5()
104 if (c->x86_model == 9 || c->x86_model == 10) { in init_amd_k5()
115 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); in init_amd_k6()
117 if (c->x86_model < 6) { in init_amd_k6()
118 /* Based on AMD doc 20734R - June 2000 */ in init_amd_k6()
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