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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
17 use the Data RAMs present within the PRU-ICSS for code execution.
22 auxiliary Transmit PRU cores called Tx_PRUs that augment the PRUs. Each RTU
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_prueth.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
12 #include <linux/dma-mapping.h>
13 #include <linux/dma/ti-cppi5.h>
19 #include <linux/io-64-nonatomic-hi-lo.h>
37 #include "../k3-cppi-desc-pool.h"
56 struct prueth *prueth = emac->prueth; in emac_get_tx_ts()
65 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); in emac_get_tx_ts()
89 !emac->tx_ts_skb[tsr.cookie]) { in tx_ts_work()
90 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", in tx_ts_work()
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H A Dicssg_prueth_sr1.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
26 #include "../k3-cppi-desc-pool.h"
34 * situation. So use Q0-Q2 as data queues and Q3 as management queue
62 config.addr_lo = cpu_to_le32(lower_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
63 config.addr_hi = cpu_to_le32(upper_32_bits(prueth->msmcram.pa)); in icssg_config_sr1()
64 config.rx_flow_id = cpu_to_le32(emac->rx_flow_id_base); /* flow id for host port */ in icssg_config_sr1()
65 config.rx_mgr_flow_id = cpu_to_le32(emac->rx_mgm_flow_id_base); /* for mgm ch */ in icssg_config_sr1()
69 index = i - PRUETH_EMAC_BUF_POOL_START_SR1; in icssg_config_sr1()
73 va = prueth->shram.va + slice * ICSSG_CONFIG_OFFSET_SLICE1; in icssg_config_sr1()
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