Searched full:addccc (Results 1 – 3 of 3) sorted by relevance
| /titanic_53/usr/src/uts/sun4v/ml/ |
| H A D | mach_subr_asm.s | 281 * ADDCCC with two source registers:
287 * the ADDCCC to obtain instructions that are complements in all but
330 * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6.
331 * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then
337 * will set the carry bit and every addccc thereafter will continue
359 #define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2
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| /titanic_53/usr/src/uts/sun4u/ml/ |
| H A D | mach_subr_asm.s | 287 * ADDCCC with two source registers:
293 * the ADDCCC to obtain instructions that are complements in all but
336 * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6.
337 * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then
343 * will set the carry bit and every addccc thereafter will continue
365 #define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2
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| /titanic_53/usr/src/lib/libdisasm/common/ |
| H A D | dis_sparc_instr.c | 1662 OVERLAY(0x18, INST("addccc", V9|V9S, 0)),
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