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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnvidia,tegra20-ac97.txt1 NVIDIA Tegra 20 AC97 controller
4 - compatible : "nvidia,tegra20-ac97"
5 - reg : Should contain AC97 controller registers location and length
6 - interrupts : Should contain AC97 interrupt
7 - resets : Must contain an entry for each entry in reset-names.
9 - reset-names : Must include the following entries:
10 - ac97
11 - dmas : Must contain an entry for each entry in clock-names.
13 - dma-names : Must include the following entries:
14 - rx
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H A Dnvidia,tegra20-ac97.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 AC97 controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-ac97
23 reset-names:
24 const: ac97
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H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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H A Dnvidia,tegra-audio-wm9712.txt4 - compatible : "nvidia,tegra-audio-wm9712"
5 - clocks : Must contain an entry for each entry in clock-names.
6 See ../clocks/clock-bindings.txt for details.
7 - clock-names : Must include the following entries:
8 - pll_a
9 - pll_a_out0
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
11 - nvidia,model : The user-visible name of this sound complex.
12 - nvidia,audio-routing : A list of the connections between audio components.
39 - nvidia,ac97-controller : The phandle of the Tegra AC97 controller
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H A Dmarvell,pxa2xx-ac97.txt3 This descriptions matches the AC97 controller found in pxa2xx and pxa3xx series.
6 - compatible: should be one of the following:
7 "marvell,pxa250-ac97"
8 "marvell,pxa270-ac97"
9 "marvell,pxa300-ac97"
10 - reg: device MMIO address space
11 - interrupts: single interrupt generated by AC97 IP
12 - clocks: input clock of the AC97 IP, refer to clock-bindings.txt
15 - pinctrl-names, pinctrl-0: refer to pinctrl-bindings.txt
16 - reset-gpios: gpio used for AC97 reset, refer to gpio.txt
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H A Dac97-bus.txt1 Generic AC97 Device Properties
3 This documents describes the devicetree bindings for an ac97 controller child
4 node describing ac97 codecs.
7 -compatible : Must be "ac97,vendor_id1,vendor_id2
10 -reg : Must be the ac97 codec number, between 0 and 3
13 ac97: sound@40500000 {
14 compatible = "marvell,pxa270-ac97";
17 reset-gpios = <&gpio 95 GPIO_ACTIVE_HIGH>;
18 #sound-dai-cells = <1>;
19 pinctrl-names = "default";
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H A Dfsl,ssi.txt4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
19 depending on the type of interrupt controller you
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H A Datmel_ac97c.txt1 * Atmel AC97 controller
4 - compatible: "atmel,at91sam9263-ac97c"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain AC97 interrupt
7 - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used
9 - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
13 compatible = "atmel,at91sam9263-ac97c";
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinctrl_ac97>;
19 ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>;
H A Dnvidia,tegra-audio-wm9712.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm9712.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm9712([-_][a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm9712
22 nvidia,audio-routing:
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H A Dnvidia,tegra-audio-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 - description: PLL A clock
17 - description: PLL A OUT0 clock
18 - description: The Tegra cdev1/extern1 clock, which feeds the card's mclk
20 clock-names:
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H A Dfsl-asoc-card.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl-asoc-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
28 - Shengjiu Wang <shengjiu.wang@nxp.com>
33 - items:
34 - enum:
35 - fsl,imx-sgtl5000
36 - fsl,imx25-pdk-sgtl5000
37 - fsl,imx53-cpuvo-sgtl5000
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H A Dingenic,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs AC97 / I2S Controller (AIC)
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dai-common.yaml#
17 pattern: '^audio-controller@'
21 - enum:
22 - ingenic,jz4740-i2s
23 - ingenic,jz4760-i2s
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dpcm030.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
13 &gpt0 { fsl,has-wdt; };
14 &gpt2 { gpio-controller; };
15 &gpt3 { gpio-controller; };
16 &gpt4 { gpio-controller; };
17 &gpt5 { gpio-controller; };
18 &gpt6 { gpio-controller; };
19 &gpt7 { gpio-controller; };
26 audioplatform: psc@2000 { /* PSC1 in ac97 mode */
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H A Dpcm032.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
5 * Copyright (C) 2006-2009 Pengutronix
11 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; };
14 &gpt4 { gpio-controller; };
15 &gpt5 { gpio-controller; };
16 &gpt6 { gpio-controller; };
17 &gpt7 { gpio-controller; };
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H A Dlite5200b.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007 Secret Lab Technologies Ltd.
11 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; };
20 compatible = "gpio-leds";
26 linux,default-trigger = "heartbeat";
40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
41 cell-index = <0>;
64 // PSC2 in ac97 mode example
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H A Dmpc5121ads.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
32 compatible = "cfi-flash";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 bank-width = <4>;
37 device-width = <2>;
42 read-only;
52 device-tree@3ec0000 {
53 label = "device-tree";
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H A Dlite5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007 Secret Lab Technologies Ltd.
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&mpc5200_pic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
25 d-cache-line-size = <32>;
26 i-cache-line-size = <32>;
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
23 uart1(cts), lcd-spi(cs1), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
40 mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
41 ac97-1(sysclko)
42 mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
[all …]
H A Dpinctrl-atlas7.txt1 CSR SiRFatlas7 pinmux controller
4 - compatible : "sirf,atlas7-ioc"
5 - reg : Address range of the pinctrl registers
9 compatible = "sirf,atlas7-ioc";
12 a_ac97_pmx: ac97@0 {
13 ac97 {
34 bias-pull-up;
41 input-schmitt-enable;
48 bias-pull-down;
55 drive-strength = <2>;
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC M2P DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
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/freebsd/sys/contrib/device-tree/Bindings/soc/cirrus/
H A Dcirrus,ep9301-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/cirrus/cirrus,ep9301-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic EP93xx Platforms System Controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 Central resources are controlled by a set of software-locked registers,
19 The System Controller (Syscon) provides:
20 - Clock control
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/freebsd/share/man/man4/
H A Dsnd_emu10kx.42 .\" Copyright (c) 2003-2007 Yuriy Tsibizov
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
60 for details), and MPU401-compatible MIDI I/O controller, which is accessible
68 .Bl -bullet -compact
94 .Bl -bullet -compact
96 Creative Sound Blaster Live!\& 24-Bit, identified by
104 .Qq Li "CA0106-DAT Audigy LS" .
106 All other Creative sound cards with -DAT chipsets.
108 All Creative X-Fi series sound cards.
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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/freebsd/sys/contrib/device-tree/src/arm/cirrus/
H A Dep93xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
11 compatible = "simple-bus";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "cirrus,ep9301-syscon", "syscon";
20 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 lan-reset-n-hog {
32 gpio-hog;
34 output-high;
35 line-name = "LAN_RESET#";
38 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
[all …]

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