| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | xlnx,versal-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
29 versal_fpga: versal-fpga {
30 compatible = "xlnx,versal-fpga";
|
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | xilinx-versal-cpm.yaml | 4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
18 - xlnx,versal-cpm-host-1.00
19 - xlnx,versal-cpm5-host
20 - xlnx,versal-cpm5-host1
21 - xlnx,versal-cpm5nc-host
79 versal {
83 compatible = "xlnx,versal-cpm-host-1.00";
110 compatible = "xlnx,versal-cpm5-host";
|
| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | xlnx,zynqmp-reset.yaml | 7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
27 For list of all valid reset indices for Versal
28 <dt-bindings/reset/xlnx-versal-resets.h>
34 - xlnx,versal-reset
35 - xlnx,versal-net-reset
|
| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | versal-net-vn-x-b2197-01-revA.dts | 3 * dts file for Xilinx Versal Net VNX board revA
13 #include "versal-net.dtsi"
14 #include "versal-net-clk.dtsi"
18 compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
19 model = "Xilinx Versal NET VNX revA";
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | xlnx,versal-net-ddrmc5.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
7 title: Xilinx Versal NET Memory Controller
14 compact and extended memory interfaces. Versal NET DDR memory controller
21 const: xlnx,versal-net-ddrmc5
39 compatible = "xlnx,versal-net-ddrmc5";
|
| H A D | xlnx,versal-ddrmc-edac.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
7 title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
15 4X memory interfaces. Versal DDR memory controller has an optional ECC support
20 const: xlnx,versal-ddrmc
51 compatible = "xlnx,versal-ddrmc";
|
| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | xlnx,versal-net-cdx.yaml | 4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
39 const: xlnx,versal-net-cdx
73 compatible = "xlnx,versal-net-cdx";
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | xlnx,versal-pinctrl.yaml | 4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
7 title: Xilinx Versal Pinctrl
17 Versal's pin configuration nodes act as a container for an arbitrary number of
28 const: xlnx,versal-pinctrl
252 compatible = "xlnx,versal-pinctrl";
|
| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | xlnx,zynqmp-rtc.yaml | 25 - xlnx,versal-rtc
26 - xlnx,versal-net-rtc
|
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | xlnx,clocking-wizard.yaml | 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
23 - xlnx,versal-clk-wizard
|
| /linux/drivers/char/hw_random/ |
| H A D | xilinx-trng.c | 3 * AMD Versal True Random Number Generator driver
274 trng->name = "Xilinx Versal Crypto Engine TRNG"; in xtrng_hwrng_register()
337 { .compatible = "xlnx,versal-trng", },
345 .name = "xlnx,versal-trng",
|
| /linux/drivers/reset/ |
| H A D | reset-zynqmp.c | 127 { .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
128 { .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, },
|
| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | dwc3-xilinx.yaml | 17 - xlnx,versal-dwc3
106 - xlnx,versal-dwc3
|
| /linux/drivers/pci/controller/ |
| H A D | pcie-xilinx-cpm.c | 3 * PCIe host controller driver for Xilinx Versal CPM DMA Bridge
659 .compatible = "xlnx,versal-cpm-host-1.00",
663 .compatible = "xlnx,versal-cpm5-host",
667 .compatible = "xlnx,versal-cpm5-host1",
671 .compatible = "xlnx,versal-cpm5nc-host",
|
| /linux/drivers/cdx/controller/ |
| H A D | cdx_controller.c | 3 * CDX host controller driver for AMD versal-net platform.
237 {.compatible = "xlnx,versal-net-cdx",},
|
| H A D | mc_cdx_pcol.h | 315 * addresses (prior to any potential IOMMU translation). For versal-net, these
629 * interrupt vector. Versal-net implementation specific limitations are that
674 * MSI data to be used by the hardware. On versal-net, only the lower 16-bits
703 * enum: MCDI command directed to versal-net. MCDI responses of this type
|
| H A D | mcdi_functions.h | 80 * @msi_data: MSI data to be used by the hardware. On versal-net, only the
|
| /linux/drivers/watchdog/ |
| H A D | xilinx_wwdt.c | 3 * Window watchdog device driver for Xilinx Versal WWDT
235 { .compatible = "xlnx,versal-wwdt", },
|
| /linux/Documentation/devicetree/bindings/ufs/ |
| H A D | amd,versal2-ufs.yaml | 7 title: AMD Versal Gen 2 UFS Host Controller
|
| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-zynqmp-qspi.yaml | 15 - xlnx,versal-qspi-1.0
|
| /linux/drivers/edac/ |
| H A D | versalnet_edac.c | 3 * AMD Versal NET memory controller driver
826 sprintf(name, "versal-net-ddrmc5-edac-%d", i); in init_one_mc()
960 { .compatible = "xlnx,versal-net-ddrmc5", },
967 .name = "versal-net-edac",
977 MODULE_DESCRIPTION("Versal NET EDAC driver");
|
| H A D | versal_edac.c | 3 * Xilinx Versal memory controller driver
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
1042 { .compatible = "xlnx,versal-ddrmc", },
|
| /linux/drivers/crypto/xilinx/ |
| H A D | zynqmp-aes-gcm.c | 854 .cra_driver_name = "versal-aes-gcm",
884 .cra_driver_name = "versal-paes-gcm",
|
| /linux/drivers/clk/zynqmp/ |
| H A D | clkc.c | 791 {.compatible = "xlnx,versal-clk"},
|
| /linux/drivers/pinctrl/ |
| H A D | pinctrl-zynqmp.c | 994 { .compatible = "xlnx,versal-pinctrl" },
|