| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-iio-timer-stm32 | 8 - "reset"
11 - "enable"
14 - "update"
18 - "compare_pulse"
21 - "OC1REF"
23 - "OC2REF"
25 - "OC3REF"
27 - "OC4REF"
32 - "OC5REF"
34 - "OC6REF"
[all …]
|
| H A D | sysfs-class-net | 35 Values vary based on the lower-level protocol used by the
54 01-80-C2-00-00-0X on a bridge device. Only values that set bits
62 0 01-80-C2-00-00-00 Bridge Group Address used for STP
63 1 01-80-C2-00-00-01 (MAC Control) 802.3 used for MAC PAUSE
64 2 01-80-C2-00-00-02 (Link Aggregation) 802.3ad
68 care when forwarding control frames e.g. 802.1X-PAE or LLDP.
89 1 physical link is up
135 the device is not usable unless some supplicant-based
193 Indicates the system-wide interface unique index identifier as a
204 Indicates the system-wide interface unique index identifier a
[all …]
|
| /linux/tools/perf/Documentation/ |
| H A D | perf-list.txt | 1 perf-list(1)
5 ----
6 perf-list - List all symbolic event types
9 --------
15 -----------
17 various perf commands with the -e option.
20 -------
21 -d::
22 --desc::
25 --no-desc::
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-t
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellde/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-t
[all...] |
| H A D | cache.json | 7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
63 "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
72 "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
81 "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
90 "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting doe
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwell/ |
| H A D | frontend.json | 11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-t
[all...] |
| /linux/drivers/comedi/drivers/ |
| H A D | comedi_8254.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 * COMEDI - Linux Control and Measurement Device Interface
20 * This module is not used directly by end-users. Rather, it is used by other
29 * sets up the module for MMIO register access; the _io version sets it
30 * up for PIO access. These functions return a pointer to a struct
33 * dev->pacer and will be freed by the comedi core during the driver
45 * I8254_MODE1 Hardware retriggerable one-shot
51 * In addition I8254_BCD and I8254_BINARY specify the counting mode:
52 * I8254_BCD BCD counting
53 * I8254_BINARY Binary counting
[all …]
|
| /linux/tools/perf/ |
| H A D | design.txt | 3 ------------------------------
7 as instructions executed, cachemisses suffered, or branches mis-predicted -
9 trigger interrupts when a threshold number of events have passed - and can
15 provides "virtual" 64-bit counters, regardless of the width of the
72 is divided into 3 bit-fields:
80 machine-specific.
119 will return -EINVAL.
121 More hw_event_types are supported as well, but they are CPU-specific
152 Counters come in two flavours: counting counters and sampling
153 counters. A "counting" counter is one that is used for counting the
[all …]
|
| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | renesas,rzg2l-gpt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
16 * Up-counting or down-counting (saw waves) or up/down-counting
26 * Registers for setting up frame cycles in each channel (with capability
31 * Starting, stopping, clearing and up/down counters in response to input
33 * Starting, clearing, stopping and up/down counters in response to a
[all …]
|
| /linux/arch/s390/kernel/ |
| H A D | perf_pai_ext.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Performance event support - Processor Activity Instrumentation Extension
48 struct pai_userdata *save; /* Area to store non-zero counters */
53 struct list_head syswide_list; /* List system-wide sampling events */
92 return -ENOMEM; in paiext_root_alloc()
101 * counting and sampling events.
103 * sampling and counting on that cpu is zero.
108 /* Free all memory allocated for event counting/sampling setup */
111 kfree(mp->mapptr->area); in paiext_free()
112 kfree(mp->mapptr->paiext_cb); in paiext_free()
[all …]
|
| /linux/Documentation/misc-devices/ |
| H A D | bh1770glc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - ROHM BH1770GLC
10 - OSRAM SFH7770
19 -----------
28 Proximity part contains IR-led driver up to 3 IR leds. The chip measures
49 -----
52 RO - shows detected chip type and version
55 RW - enable / disable chip
57 Uses counting logic
59 - 1 enables the chip
[all …]
|
| /linux/tools/testing/selftests/powerpc/pmu/ |
| H A D | per_event_excludes.c | 1 // SPDX-License-Identifier: GPL-2.0-only
20 * Test that per-event excludes work.
32 * counts don't match up. in per_event_excludes()
37 e->attr.disabled = 1; in per_event_excludes()
42 e->attr.disabled = 1; in per_event_excludes()
43 e->attr.exclude_user = 1; in per_event_excludes()
44 e->attr.exclude_hv = 1; in per_event_excludes()
49 e->attr.disabled = 1; in per_event_excludes()
50 e->attr.exclude_user = 1; in per_event_excludes()
51 e->attr.exclude_kernel = 1; in per_event_excludes()
[all …]
|
| /linux/Documentation/admin-guide/perf/ |
| H A D | hisi-pmu.rst | 11 (CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
12 called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
48 ------------------------------------------
50 ------------------------------------------
52 ------------------------------------------
[all …]
|
| /linux/kernel/locking/ |
| H A D | semaphore.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file implements counting semaphores.
7 * A counting semaphore may be acquired 'n' times before sleeping.
8 * See mutex.c for single-acquisition sleeping locks which enforce
16 * down_trylock() and up() can be called from interrupt context, so we
23 * The ->count variable represents how many more tasks can acquire this
48 WRITE_ONCE((sem)->last_holder, (unsigned long)current); in hung_task_sem_set_holder()
53 if (READ_ONCE((sem)->last_holder) == (unsigned long)current) in hung_task_sem_clear_if_holder()
54 WRITE_ONCE((sem)->last_holder, 0UL); in hung_task_sem_clear_if_holder()
59 return READ_ONCE(sem->last_holder); in sem_last_holder()
[all …]
|
| /linux/Documentation/devicetree/bindings/arc/ |
| H A D | pct.txt | 3 The ARC700 can be configured with a pipeline performance monitor for counting
5 are 100+ hardware conditions dynamically mapped to up to 32 counters
13 - compatible : should contain
14 "snps,arc700-pct"
19 compatible = "snps,arc700-pct";
|
| H A D | snps,archs-pct.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arc/snps,archs-pct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Aryabhatta Dey <aryabhattadey35@gmail.com>
13 The ARC HS can be configured with a pipeline performance monitor for counting
15 are 100+ hardware conditions dynamically mapped to up to 32 counters.
20 const: snps,archs-pct
29 - compatible
30 - reg
[all …]
|
| /linux/fs/bfs/ |
| H A D | bfs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2018 Tigran Aivazian <aivazian.tigran@gmail.com>
11 /* In theory BFS supports up to 512 inodes, numbered from 2 (for /) up to 513 inclusive.
13 …l with ENOSPC in bfs_add_entry(): the root directory cannot contain so many entries, counting '..'.
14 …So, mkfs.bfs(8) should really limit its -N option to 511 and not 512. For now, we just print a war…
15 if a filesystem is mounted with such "impossible to fill up" number of inodes */
19 * BFS file system in-core superblock info
32 * BFS file system in-core inode info
43 return sb->s_fs_info; in BFS_SB()
53 printk(KERN_ERR "BFS-fs: %s(): " format, __func__, ## args)
|
| /linux/arch/microblaze/kernel/ |
| H A D | head.S | 2 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2007-2009 PetaLogix
7 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
12 * Low-level exception handers, MMU support, and rewrite.
15 * Copyright (c) 1998-1999 TiVo, Inc.
72 * r8 == 0 - msr instructions are implemented
73 * r8 != 0 - msr instructions are not implemented
76 msrclr r8, 0 /* clear nothing - just read msr for test */
82 is broken or non-existent */
86 /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */
[all …]
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| /linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/ |
| H A D | irqsrcs_dcn_1_0.h | 192 #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GEN…
309 #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete…
312 #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete…
315 #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete…
318 #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete…
321 #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete…
324 #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete…
420 #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt D…
423 #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt D…
426 #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt D…
[all …]
|
| /linux/Documentation/admin-guide/device-mapper/ |
| H A D | dm-flakey.rst | 2 dm-flakey
10 <up interval> seconds, then exhibits unreliable behaviour for <down
13 Also, consider using this in combination with the dm-delay target too,
18 ----------------
22 <dev path> <offset> <up interval> <down interval> \
28 Full pathname to the underlying block-device, or a
29 "major:minor" device-number.
32 <up interval>:
60 Counting starts at 1, to replace the first byte.
65 The value (from 0-255) to write.
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | frontend.json | 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
58 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | frontend.json | 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
58 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | frontend.json | 7 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
16 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
46 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
58 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to …
97 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
104 …er an interval where the front-end delivered no uops for a period of at least 1 cycle which was no…
[all …]
|
| /linux/Documentation/core-api/ |
| H A D | local_ops.rst | 51 their UP variant must be kept. It typically means removing LOCK prefix (on
53 not have a different behavior between SMP and UP, including
54 ``asm-generic/local.h`` in your architecture's ``local.h`` is sufficient.
72 different CPU between getting the per-cpu variable and doing the
78 -rt kernels.
98 Counting chapter
101 Counting is done on all the bits of a signed long.
110 If you are already in a preemption-safe context, you can use
139 /* test-local.c
|