Searched +full:u54 +full:- +full:mc +full:- +full:rvcoreip (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause4 ---5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: SiFive Platform-Level Interrupt Controller (PLIC)11 SiFive SoCs and other RISC-V SoCs include an implementation of the12 Platform-Level Interrupt Controller (PLIC) high-level specification in13 the RISC-V Privileged Architecture specification. The PLIC connects all18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two21 Each interrupt can be enabled on per-context basis. Any context can claim[all …]
1 // SPDX-License-Identifier: GPL-2.06 #define pr_fmt(fmt) "riscv-plic: " fmt25 * This driver implements a version of the RISC-V PLIC with the actual layout28 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf30 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is31 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged102 u32 __iomem *base = handler->enable_base; in __plic_toggle()114 handler->enable_save[group] = value; in __plic_toggle()122 raw_spin_lock_irqsave(&handler->enable_lock, flags); in plic_toggle()124 raw_spin_unlock_irqrestore(&handler->enable_lock, flags); in plic_toggle()[all …]