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/linux/rust/kernel/net/
H A Dphy.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Network PHY device.
7 //! C headers: [`include/linux/phy.h`](srctree/include/linux/phy.h).
14 /// PHY state machine states.
18 /// Some of PHY drivers access to the state of PHY's software state machine.
20 /// [`enum phy_state`]: srctree/include/linux/phy.h
23 /// PHY device and driver are not ready for anything.
25 /// PHY is ready to send and receive packets.
27 /// PHY is up, but no polling or interrupts are done.
29 /// PHY is up, but is in an error state.
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/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
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H A Dmediatek,mt7988-xfi-tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7988 XFI T-PHY
10 - Daniel Golle <daniel@makrotopia.org>
13 The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
15 MediaTek's 10G-capabale MT7988 SoC.
20 const: mediatek,mt7988-xfi-tphy
27 - description: XFI PHY clock
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H A Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <jstephan@baylibre.com>
12 - Andy Hsieh <andy.hsieh@mediatek.com>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
23 - mediatek,mt8365-csi-rx
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/linux/drivers/usb/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
32 tristate "Keystone USB PHY Driver"
36 Enable this to support Keystone USB phy. This driver provides
37 interface to interact with USB 2.0 and USB 3.0 PHY that is part
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
47 phy programming such as ISP1x04 etc.
53 tristate "AM335x USB PHY Driver"
60 This driver provides PHY support for that phy which part for the
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H A Dphy-gpio-vbus-usb.c1 // SPDX-License-Identifier: GPL-2.0
3 * gpio-vbus.c - simple GPIO VBUS sensing driver for B peripheral devices
33 struct usb_phy phy; member
60 struct regulator *vbus_draw = gpio_vbus->vbus_draw; in set_vbus_draw()
67 enabled = gpio_vbus->vbus_draw_enabled; in set_vbus_draw()
74 gpio_vbus->vbus_draw_enabled = 1; in set_vbus_draw()
81 gpio_vbus->vbus_draw_enabled = 0; in set_vbus_draw()
84 gpio_vbus->mA = mA; in set_vbus_draw()
89 return gpiod_get_value(gpio_vbus->vbus_gpiod); in is_vbus_powered()
98 if (!gpio_vbus->phy.otg->gadget) in gpio_vbus_work()
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/linux/net/mac80211/
H A Ddebugfs_sta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2003-2005 Devicescape Software, Inc.
6 * Copyright 2013-2014 Intel Mobile Communications GmbH
8 * Copyright (C) 2018 - 2023 Intel Corporation
17 #include "driver-ops.h"
26 struct sta_info *sta = file->private_data; \
28 format_string, sta->field); \
90 char *end = buf + sizeof(buf) - 1; in sta_flags_read()
91 struct sta_info *sta = file->private_data; in sta_flags_read()
98 pos += scnprintf(pos, end - pos, "%s\n", in sta_flags_read()
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/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/phy/phy.h>
56 struct phy *phy; member
61 static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg) in u2_phy_w32() argument
63 writel(val, phy->base + reg); in u2_phy_w32()
66 static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg) in u2_phy_r32() argument
68 return readl(phy->base + reg); in u2_phy_r32()
71 static void ralink_usb_phy_init(struct ralink_usb_phy *phy) in ralink_usb_phy_init() argument
73 u2_phy_r32(phy, OFS_U2_PHY_AC2); in ralink_usb_phy_init()
74 u2_phy_r32(phy, OFS_U2_PHY_ACR0); in ralink_usb_phy_init()
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip emmc PHY driver
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
15 #include <linux/phy/phy.h>
20 * The higher 16-bit of this register is used for write protection
93 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) in rockchip_emmc_phy_power() argument
95 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); in rockchip_emmc_phy_power()
106 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6, in rockchip_emmc_phy_power()
111 regmap_write(rk_phy->reg_base, in rockchip_emmc_phy_power()
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/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
216 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
242 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
267 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
300 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy) in ti_pipe3_get_dpll_params() argument
303 struct pipe3_dpll_map *dpll_map = phy->dpll_map; in ti_pipe3_get_dpll_params()
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/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
12 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
14 /* PHY 1000 MII Register/Bit Definitions */
15 /* PHY Registers defined by IEEE */
18 #define PHY_ID1 0x02 /* Phy Id Register (word 1) */
19 #define PHY_ID2 0x03 /* Phy Id Register (word 2) */
25 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */
26 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */
28 #define PHY_PHYSP_CONTROL 0x10 /* PHY Specific Control Register */
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
11 static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy) in msm_hdmi_phy_resource_init() argument
13 struct hdmi_phy_cfg *cfg = phy->cfg; in msm_hdmi_phy_resource_init()
14 struct device *dev = &phy->pdev->dev; in msm_hdmi_phy_resource_init()
17 phy->regs = devm_kcalloc(dev, cfg->num_regs, sizeof(phy->regs[0]), in msm_hdmi_phy_resource_init()
19 if (!phy->regs) in msm_hdmi_phy_resource_init()
20 return -ENOMEM; in msm_hdmi_phy_resource_init()
22 phy->clks = devm_kcalloc(dev, cfg->num_clks, sizeof(phy->clks[0]), in msm_hdmi_phy_resource_init()
24 if (!phy->clks) in msm_hdmi_phy_resource_init()
25 return -ENOMEM; in msm_hdmi_phy_resource_init()
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/linux/drivers/scsi/aic94xx/
H A Daic94xx_hwi.c1 // SPDX-License-Identifier: GPL-2.0-only
23 /* ---------- Initialization ---------- */
28 if (asd_ha->hw_prof.sas_addr[0]) in asd_get_user_sas_addr()
31 return sas_request_addr(asd_ha->sas_ha.shost, in asd_get_user_sas_addr()
32 asd_ha->hw_prof.sas_addr); in asd_get_user_sas_addr()
40 if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0) in asd_propagate_sas_addr()
42 /* Set a phy's address only if it has none. in asd_propagate_sas_addr()
44 ASD_DPRINTK("setting phy%d addr to %llx\n", i, in asd_propagate_sas_addr()
45 SAS_ADDR(asd_ha->hw_prof.sas_addr)); in asd_propagate_sas_addr()
46 memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, in asd_propagate_sas_addr()
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H A Daic94xx_scb.c1 // SPDX-License-Identifier: GPL-2.0-only
19 /* ---------- EMPTY SCB ---------- */
36 static void get_lrate_mode(struct asd_phy *phy, u8 oob_mode) in get_lrate_mode() argument
38 struct sas_phy *sas_phy = phy->sas_phy.phy; in get_lrate_mode()
42 /* FIXME: sas transport class doesn't have this */ in get_lrate_mode()
43 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
44 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS; in get_lrate_mode()
47 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
48 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS; in get_lrate_mode()
51 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS; in get_lrate_mode()
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/linux/drivers/scsi/pm8001/
H A Dpm8001_hwi.c2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
18 * 3. Neither the names of the above-listed copyright holders nor the names
48 * read_main_config_table - read the configure table and save it.
53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; in read_main_config_table()
54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = in read_main_config_table()
56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = in read_main_config_table()
58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = in read_main_config_table()
60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = in read_main_config_table()
62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = in read_main_config_table()
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/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay eMMC PHY driver
14 #include <linux/phy/phy.h>
18 /* eMMC/SD/SDIO core/phy configuration registers */
53 static int keembay_emmc_phy_power(struct phy *phy, bool on_off) in keembay_emmc_phy_power() argument
55 struct keembay_emmc_phy *priv = phy_get_drvdata(phy); in keembay_emmc_phy_power()
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
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/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
152 #define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
160 { PL_C_MIN, SLOW_C_MIN }, /* min t. to remain Connect State */
161 { PL_TL_MIN, SLOW_TL_MIN }, /* min t. to transmit a Line State */
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/linux/drivers/net/phy/
H A Dphy_device.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Also contains generic PHY driver
29 #include <linux/phy.h>
33 #include <linux/pse-pd/pse.h>
43 MODULE_DESCRIPTION("PHY library");
252 put_device(&phydev->mdio.dev); in phy_device_free()
266 fwnode_handle_put(dev->fwnode); in phy_device_release()
294 struct device_driver *drv = phydev->mdio.dev.driver; in mdio_bus_phy_may_suspend()
296 struct net_device *netdev = phydev->attached_dev; in mdio_bus_phy_may_suspend()
298 if (!drv || !phydrv->suspend) in mdio_bus_phy_may_suspend()
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/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
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/linux/arch/powerpc/boot/dts/fsl/
H A Dppa8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PPA8548 Device Tree Source (36-bit address map)
7 * MPC8548 CDS Device Tree Source (36-bit address map)
11 /include/ "mpc8548si-pre.dtsi"
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&mpic>;
35 /* ppa8548 board doesn't support PCI */
40 /* ppa8548 board doesn't support PCI */
45 /* ppa8548 board doesn't support PCI */
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H A Dp1020utm-pc.dtsi2 * P1020 UTM-PC Device Tree Source stub (no addresses or top-level ranges)
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
67 label = "NOR U-Boot Image";
68 read-only;
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/linux/Documentation/networking/
H A Dphy-link-topology.rst1 .. SPDX-License-Identifier: GPL-2.0
5 PHY link topology
11 The PHY link topology representation in the networking stack aims at representing
19 +-----------------------+ +----------+ +--------------+
21 | MAC | ------ | PHY | ---- | Port | ---... to LP
22 +-----------------------+ +----------+ +--------------+
25 Commands that needs to configure the PHY will go through the net_device.phydev
26 field to reach the PHY and perform the relevant configuration.
37 +-----+ SGMII +------------+
38 | MAC | ------- | SFP Module |
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/linux/drivers/net/wireless/mediatek/mt76/
H A Dtx.c1 // SPDX-License-Identifier: ISC
11 if (!txq->sta) in mt76_txq_get_qid()
14 return txq->ac; in mt76_txq_get_qid()
20 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in mt76_tx_check_agg_ssn()
25 if (!sta || !ieee80211_is_data_qos(hdr->frame_control) || in mt76_tx_check_agg_ssn()
26 !ieee80211_is_data_present(hdr->frame_control)) in mt76_tx_check_agg_ssn()
29 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; in mt76_tx_check_agg_ssn()
30 txq = sta->txq[tid]; in mt76_tx_check_agg_ssn()
31 mtxq = (struct mt76_txq *)txq->drv_priv; in mt76_tx_check_agg_ssn()
32 if (!mtxq->aggr) in mt76_tx_check_agg_ssn()
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/linux/drivers/usb/chipidea/
H A Dci_hdrc_tegra.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <linux/usb/phy.h>
31 struct usb_phy *phy; member
77 .compatible = "nvidia,tegra20-ehci",
80 .compatible = "nvidia,tegra30-ehci",
83 .compatible = "nvidia,tegra20-udc",
86 .compatible = "nvidia,tegra30-udc",
89 .compatible = "nvidia,tegra114-udc",
92 .compatible = "nvidia,tegra124-udc",
108 dev_err(dev, "can't get ehci reset: %pe\n", rst); in tegra_usb_reset_controller()
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