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/linux/drivers/scsi/isci/
H A Dprobe_roms.h228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
238 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
239 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
240 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
246 * NOTE: Max spread for SAS down-spreading +0 /
249 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
250 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
252 * NOTE: Max spread for SAS center-spreading +2300 /
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml57 optional child node can be used to specify spread
63 spread-spectrum:
67 spread-spectrum-center:
99 spread-spectrum = <4>;
100 spread-spectrum-center;
H A Dmediatek,mt8186-fhctl.yaml7 title: MediaTek frequency hopping and spread spectrum clocking control
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
35 description: The percentage of spread spectrum clocking for one PLL.
H A Drenesas,9series.yaml59 renesas,out-spread-spectrum:
62 description: Output clock down spread in pcm (1/1000 of percent)
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf134 (RO) Presents SSC (spread spectrum clock) information for EMI
140 [7:0] Sets clock spectrum spread percentage:
142 1 LSB = 0.1% increase in spread (for
144 1 LSB = 0.2% increase in spread (for
146 [8] When set to 1, enables spread
153 (Spread spectrum clock) range
155 to spread waveform
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst214 which is compensated by adjusting Spread spectrum percent. This helps
241 Set the FIVR spread spectrum clocking percentage
244 Enable/disable of the FIVR spread spectrum clocking feature
309 Sets DLVR spread spectrum percent value.
312 Specifies how frequencies are spread using spread spectrum.
313 0: Down spread,
314 1: Spread in the Center.
/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt40 regulator-coupled-max-spread = <170000 550000>;
50 regulator-coupled-max-spread = <170000 550000>;
60 regulator-coupled-max-spread = <550000 550000>;
/linux/drivers/clk/
H A Dclk-renesas-pcie.c230 /* Output clock spread spectrum */ in rs9_get_common_config()
231 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); in rs9_get_common_config()
233 if (ssc == 100000) /* 100% ... no spread (default) */ in rs9_get_common_config()
235 else if (ssc == 99750) /* -0.25% ... down spread */ in rs9_get_common_config()
237 else if (ssc == 99500) /* -0.50% ... down spread */ in rs9_get_common_config()
241 "Invalid renesas,out-spread-spectrum value\n"); in rs9_get_common_config()
/linux/Documentation/misc-devices/
H A Dics932s401.rst25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h65 * Display Port HW De spread of Reference Clock related Parameters structure
70 /* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/
96 /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/
/linux/lib/zstd/common/
H A Dfse_decompress.c76 BYTE* spread = (BYTE*)(symbolNext + maxSymbolValue + 1); in FSE_buildDTable_internal() local
104 /* Spread symbols */ in FSE_buildDTable_internal()
122 MEM_write64(spread + pos, sv); in FSE_buildDTable_internal()
124 MEM_write64(spread + pos + i, sv); in FSE_buildDTable_internal()
129 /* Now we spread those positions across the table. in FSE_buildDTable_internal()
144 tableDecode[uPosition].symbol = spread[s + u]; in FSE_buildDTable_internal()
/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml60 fsl,no-spread-spectrum:
62 description: if present, disable spread-spectrum clocking on the SATA link.
/linux/kernel/cgroup/
H A Dcpuset-v1.c207 * update task's spread flag if cpuset's page/slab spread flag is set
230 * cpuset1_update_tasks_flags - update the spread flags of tasks in the cpuset.
231 * @cs: the cpuset in which each task's spread flags needs to be changed
233 * Iterate through each task of @cs updating its spread flags. As this
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h906 // SECTION: Clock Spread Spectrum
908 // GFXCLK PLL Spread Spectrum
913 // GFXCLK DFLL Spread Spectrum
918 // UCLK Spread Spectrum
922 // FCLK Spread Spectrum
949 // UCLK Spread Spectrum
1267 // SECTION: Clock Spread Spectrum
1269 // GFXCLK PLL Spread Spectrum
1274 // GFXCLK DFLL Spread Spectrum
1279 // UCLK Spread Spectrum
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c214 * It toggles spread spectrum PLL output and sets the bindings of PLLs in nv04_dfp_prepare_sel_clk()
223 * bit 0 NVClk spread spectrum on/off in nv04_dfp_prepare_sel_clk()
224 * bit 2 MemClk spread spectrum on/off in nv04_dfp_prepare_sel_clk()
225 * bit 4 PixClk1 spread spectrum on/off toggle in nv04_dfp_prepare_sel_clk()
226 * bit 6 PixClk2 spread spectrum on/off toggle in nv04_dfp_prepare_sel_clk()
231 * maybe a different spread mode in nv04_dfp_prepare_sel_clk()
233 * The logic behind turning spread spectrum on/off in the first place, in nv04_dfp_prepare_sel_clk()
/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h213 /* Input: Enable spread spectrum */
285 /* 1 = Center Spread; 0 = down spread */
H A Dddc_service_types.h103 /* support for Spread Spectrum(SS) */
105 /* DP link settings (laneCount, linkRate, Spread) */
/linux/lib/
H A Dgroup_cpus.c267 * number of groups we just spread the groups across the nodes. in __group_cpus_evenly()
307 /* Spread allocated groups on CPUs of the current node */ in __group_cpus_evenly()
373 * spread can observe consistent 'cpu_present_mask' without holding in group_cpus_evenly()
380 * from API user viewpoint since 2-stage spread is sort of in group_cpus_evenly()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-quartzpro64.dts509 regulator-coupled-max-spread = <10000>;
567 regulator-coupled-max-spread = <10000>;
836 regulator-coupled-max-spread = <10000>;
851 regulator-coupled-max-spread = <10000>;
866 regulator-coupled-max-spread = <10000>;
894 regulator-coupled-max-spread = <10000>;
910 regulator-coupled-max-spread = <10000>;
938 regulator-coupled-max-spread = <10000>;
H A Drk3588-evb1-v10.dts578 regulator-coupled-max-spread = <10000>;
632 regulator-coupled-max-spread = <10000>;
882 regulator-coupled-max-spread = <10000>;
896 regulator-coupled-max-spread = <10000>;
910 regulator-coupled-max-spread = <10000>;
936 regulator-coupled-max-spread = <10000>;
951 regulator-coupled-max-spread = <10000>;
977 regulator-coupled-max-spread = <10000>;
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi57 regulator-coupled-max-spread = <300000>;
134 regulator-coupled-max-spread = <300000>;
H A Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi70 regulator-coupled-max-spread = <300000>;
83 regulator-coupled-max-spread = <300000>;
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c48 * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
51 * Reads from VBIOS the XGMI spread spectrum info and saves it within
/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()

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