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/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
38 * struct intel_function - Description about a function
48 * struct intel_padgroup - Hardware pad group information
67 * enum - Special treatment for GPIO base in pad group
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
80 * struct intel_community - Intel pin community description
100 * @pad_map: Optional non-linear mapping of the pads
145 #define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ argument
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/linux/drivers/clk/bcm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
70 Enable common clock framework support for the Broadcom Cygnus SoC
79 SoC
96 Enable common clock framework support for the Broadcom Northstar 2 SoC
104 Enable common clock framework support for the Broadcom Stingray SoC
111 dependent clocks
/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst1 .. SPDX-License-Identifier: GPL-2.0
32 functions of the driver includes re-configuring AC timing
38 DDR device details and other board dependent and SoC dependent
41 - DDR device details: 'struct ddr_device_info'
42 - Device AC timings: 'struct lpddr2_timings' and 'struct lpddr2_min_tck'
43 - Custom configurations: customizable policy options through
45 - IP revision
46 - PHY type
53 - freq_pre_notify_handling()
54 - freq_post_notify_handling()
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H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
16 GPMC is found on Texas Instruments SoC's (OMAP based)
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
172 Many of gpmc timings are dependent on other gpmc timings (a few
173 gpmc timings purely dependent on other gpmc timings, a reason that
/linux/drivers/thermal/st/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 functionalities and to access to SoC sensor functionalities. This
23 configuration is fully dependent of MACH_STM32MP157.
/linux/Documentation/devicetree/bindings/reset/
H A Dimg,pistachio-reset.txt5 disable individual IP blocks within the Pistachio SoC using "soft reset"
6 control bits found in the Pistachio SoC top level registers.
8 The actual action taken when soft reset is asserted is hardware dependent.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
29 #clock-cells = <1>;
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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H A Dst,stih407-picophyreset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
14 disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
15 the STi family SoC system configuration registers.
17 The actual action taken when softreset is asserted is hardware dependent.
24 const: st,stih407-picophyreset
26 '#reset-cells':
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H A Dst,stih407-powerdown.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/st,stih407-powerdown.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@st.com>
14 disable on-chip peripheral controllers such as USB and SATA, using
15 "powerdown" control bits found in the STi family SoC system configuration
19 The actual action taken when powerdown is asserted is hardware dependent.
26 const: st,stih407-powerdown
28 '#reset-cells':
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H A Dst,sti-softreset.txt5 disable on-chip peripheral controllers such as USB and SATA, using
6 "softreset" control bits found in the STi family SoC system configuration
9 The actual action taken when softreset is asserted is hardware dependent.
18 - compatible: Should be "st,stih407-softreset";
19 - #reset-cells: 1, see below
23 softreset: softreset-controller {
24 #reset-cells = <1>;
25 compatible = "st,stih407-softreset";
44 include/dt-bindings/reset/stih407-resets.h
/linux/Documentation/devicetree/bindings/soc/loongson/
H A Dloongson,ls2k-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 Power Manager controller
10 - Yinbo Zhu <zhuyinbo@loongson.cn>
15 - items:
16 - const: loongson,ls2k0500-pmc
17 - const: syscon
18 - items:
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/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt1 STMicroelectronics SoC DWMAC glue layer controller
10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
14 register available on STiH407 SoC.
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
23 retimeing tx lines. This is totally board dependent and can take one of the
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H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/linux/Documentation/sound/kernel-api/
H A Dalsa-driver-api.rst9 ---------------
10 .. kernel-doc:: sound/core/init.c
13 -----------------
14 .. kernel-doc:: sound/core/device.c
17 ---------------------------------------
18 .. kernel-doc:: sound/core/sound.c
21 -------------------------
22 .. kernel-doc:: sound/core/memory.c
23 .. kernel-doc:: sound/core/memalloc.c
30 --------
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/linux/arch/arm/mach-omap2/
H A Dclockdomain.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2008-2011 Texas Instruments, Inc.
6 * Copyright (C) 2008-2011 Nokia Corporation
22 #include <linux/clk-provider.h>
29 #include "soc.h"
56 if (!strcmp(name, temp_clkdm->name)) { in _clkdm_lookup()
66 * _clkdm_register - register a clockdomain
70 * Returns -EINVAL if given a null pointer, -EEXIST if a clockdomain is
77 if (!clkdm || !clkdm->name) in _clkdm_register()
78 return -EINVAL; in _clkdm_register()
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H A Dprm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
76 * prm_ll_data: function pointers to SoC-specific implementations of
92 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
94 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
105 * done by the SoC specific individual handlers.
113 int nr_irq = prcm_irq_setup->nr_regs * 32; in omap_prcm_irq_handler()
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H A Dopp4xxx_data.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2012 Texas Instruments Incorporated - https://www.ti.com/
9 * Copyright (C) 2010-2011 Nokia Corporation.
15 #include "soc.h"
22 * voltage dependent data for each VDD.
/linux/Documentation/devicetree/bindings/mtd/
H A Dorion-nand.txt1 NAND support for Marvell Orion SoC platforms
4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
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/linux/Documentation/devicetree/bindings/dma/
H A Dsocionext,uniphier-mio-dmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Masahiro Yamada <yamada.masahiro@socionext.com>
17 - $ref: dma-controller.yaml#
21 const: socionext,uniphier-mio-dmac
29 The number of interrupt lines is SoC-dependent.
37 '#dma-cells':
42 - compatible
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/linux/Documentation/power/powercap/
H A Ddtpm.rst1 .. SPDX-License-Identifier: GPL-2.0
7 On the embedded world, the complexity of the SoC leads to an
46 SoC
48 `-- pkg
50 |-- pd0 (cpu0-3)
52 `-- pd1 (cpu4-5)
56 SoC (400mW - 3100mW)
58 `-- pkg (400mW - 3100mW)
60 |-- pd0 (100mW - 700mW)
62 `-- pd1 (300mW - 2400mW)
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/linux/sound/soc/intel/common/
H A Dsof-function-topology-lib.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 #include <sound/soc.h>
13 #include <sound/soc-acpi.h>
14 #include "sof-function-topology-lib.h"
33 struct snd_soc_acpi_mach_params mach_params = mach->mach_params; in sof_sdw_get_tplg_files()
43 ret = sscanf(mach->sof_tplg_filename, "sof-%3s-*.tplg", platform); in sof_sdw_get_tplg_files()
45 dev_err(card->dev, "Invalid platform name %s of tplg %s\n", in sof_sdw_get_tplg_files()
46 platform, mach->sof_tplg_filename); in sof_sdw_get_tplg_files()
47 return -EINVAL; in sof_sdw_get_tplg_files()
53 dev_dbg(card->dev, "dai_link %s id %d\n", dai_link->name, dai_link->id); in sof_sdw_get_tplg_files()
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/linux/drivers/gpu/drm/amd/include/
H A Dkgd_pp_interface.h170 PP_SMC_POWER_PROFILE_UNKNOWN = -1,
240 * APU power is managed to system-level requirements through the PPT
250 * enum pp_power_limit_level - Used to query the power limits
258 PP_PWR_LIMIT_MIN = -1,
265 * enum pp_power_type - Used to specify the type of the requested power
278 XGMI_PLPD_NONE = -1,
286 PP_PM_POLICY_NONE = -1,
679 /* Throttle status (ASIC dependent) */
788 /* Energy (15.259uJ (2^-16) units) */
861 /* Energy (15.259uJ (2^-16) units) */
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/linux/Documentation/devicetree/bindings/phy/
H A Dsamsung,usb2-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 meaning is compatible dependent. For the currently supported SoCs (Exynos4210
18 0 - USB device ("device"),
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/linux/Documentation/driver-api/thermal/
H A Dcpu-idle-cooling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------
10 Under certain circumstances a SoC can reach a critical temperature
12 control. When the SoC has to stabilize the temperature, the kernel can
26 budget lower than the requested one and under-utilize the CPU, thus
27 losing performance. In other words, one OPP under-utilizes the CPU
33 ----------
36 duration in a controlled period, the SoC temperature will
58 ---------------
78 |------- -------
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/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
16 - enum:
17 - fsl,imx95-flexcan
18 - fsl,imx93-flexcan
19 - fsl,imx8qm-flexcan
20 - fsl,imx8mp-flexcan
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