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/linux/Documentation/devicetree/bindings/soc/starfive/
H A Dstarfive,jh7110-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
19 - items:
20 - const: starfive,jh7110-sys-syscon
21 - const: syscon
22 - const: simple-mfd
23 - items:
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dstarfive,jh7110-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
25 - items:
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H A Dnuvoton,ma35d1-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nuvoton,ma35d1-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui-Ping Chen <hpchen0nvt@gmail.com>
15 - nuvoton,ma35d1-usb2-phy
17 "#phy-cells":
23 nuvoton,sys:
26 phandle to syscon for checking the PHY clock status.
29 - compatible
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/linux/Documentation/devicetree/bindings/clock/
H A Darm,syscon-icst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
38 integratorap-cm
41 integratorap-sys
44 integratorap-pci 14 1 14
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H A Dmediatek,mt8192-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
19 - enum:
20 - mediatek,mt8192-topckgen
21 - mediatek,mt8192-infracfg
22 - mediatek,mt8192-pericfg
23 - mediatek,mt8192-apmixedsys
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H A Dmediatek,mt8195-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
27 - enum:
28 - mediatek,mt8195-topckgen
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H A Dstarfive,jh7110-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 registers in the sys syscon. So the PLLs node should be a child of
13 SYS-SYSCON node.
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
22 const: starfive,jh7110-pll
28 '#clock-cells':
31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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H A Dmediatek,mt8186-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
29 - enum:
30 - mediatek,mt8186-mcusys
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H A Dmediatek,mt8365-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8365-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Markus Schneider-Pargmann <msp@baylibre.com>
20 - enum:
21 - mediatek,mt8365-topckgen
22 - mediatek,mt8365-infracfg
23 - mediatek,mt8365-apmixedsys
24 - mediatek,mt8365-pericfg
[all …]
H A Dmediatek,mt8188-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Garmin Chang <garmin.chang@mediatek.com>
14 PLLs -->
15 dividers -->
17 -->
29 - enum:
30 - mediatek,mt8188-apmixedsys
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/linux/Documentation/devicetree/bindings/mfd/
H A Dsyscon.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 represent as any specific type of device. The typical use-case is
13 for some other node's driver, or platform-specific code, to acquire
14 a reference to the syscon node (e.g. by phandle, node path, or
20 - Lee Jones <lee@kernel.org>
24 # syscon fallback.
30 - airoha,en7581-pbus-csr
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3528-ioc-grf
19 - rockchip,rk3528-vo-grf
20 - rockchip,rk3528-vpu-grf
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/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux/drivers/phy/starfive/
H A Dphy-jh7110-usb.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mfd/syscon.h>
42 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive()
43 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
49 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
63 return -EINVAL; in usb2_phy_set_mode()
66 if (mode != phy->mode) { in usb2_phy_set_mode()
67 dev_dbg(&_phy->dev, "Changing phy to %d\n", mode); in usb2_phy_set_mode()
68 phy->mode = mode; in usb2_phy_set_mode()
73 regmap_update_bits(phy->sys_syscon, SYSCON_USB_SPLIT_OFFSET, in usb2_phy_set_mode()
[all …]
/linux/drivers/clk/at91/
H A Dclk-system.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
10 #include <linux/mfd/syscon.h>
43 struct clk_system *sys = to_clk_system(hw); in clk_system_prepare() local
45 regmap_write(sys->regmap, AT91_PMC_SCER, 1 << sys->id); in clk_system_prepare()
47 if (!is_pck(sys->id)) in clk_system_prepare()
50 while (!clk_system_ready(sys->regmap, sys->id)) in clk_system_prepare()
58 struct clk_system *sys = to_clk_system(hw); in clk_system_unprepare() local
60 regmap_write(sys->regmap, AT91_PMC_SCDR, 1 << sys->id); in clk_system_unprepare()
65 struct clk_system *sys = to_clk_system(hw); in clk_system_is_prepared() local
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/linux/drivers/mfd/
H A Daltera-sysmgr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019, Intel Corporation.
7 * Based on syscon driver.
10 #include <linux/arm-smccc.h>
13 #include <linux/mfd/altera-sysmgr.h>
14 #include <linux/mfd/syscon.h>
22 * struct altr_sysmgr - Altera SOCFPGA System Manager
108 return ERR_PTR(-ENODEV); in altr_sysmgr_regmap_lookup_by_phandle()
116 return ERR_PTR(-EPROBE_DEFER); in altr_sysmgr_regmap_lookup_by_phandle()
120 return sysmgr->regmap; in altr_sysmgr_regmap_lookup_by_phandle()
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dimg-pwm.txt4 - compatible: Should be "img,pistachio-pwm"
5 - reg: Should contain physical base address and length of pwm registers.
6 - clocks: Must contain an entry for each entry in clock-names.
7 See ../clock/clock-bindings.txt for details.
8 - clock-names: Must include the following entries.
9 - pwm: PWM operating clock.
10 - sys: PWM system interface clock.
11 - #pwm-cells: Should be 2. See pwm.yaml in this directory for the
13 - img,cr-periph: Must contain a phandle to the peripheral control
14 syscon node which contains PWM control registers.
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
10 hdmi1_sound: hdmi1-sound {
11 compatible = "simple-audio-card";
12 simple-audio-card,format = "i2s";
13 simple-audio-card,mclk-fs = <128>;
14 simple-audio-card,name = "hdmi1";
17 simple-audio-card,codec {
18 sound-dai = <&hdmi1>;
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
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H A Drk3576.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dimg,pistachio-gptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/img,pistachio-gptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pistachio general-purpose timer
10 - Ezequiel Garcia <ezequiel.garcia@imgtec.com>
14 const: img,pistachio-gptimer
21 - description: Timer0 interrupt
22 - description: Timer1 interrupt
23 - description: Timer2 interrupt
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Damlogic,meson-gx-pwrc.txt7 ----------------
13 power-domain.yaml
16 ---------------------
19 - compatible: should be one of the following :
20 - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
21 - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
22 - #power-domain-cells: should be 0
23 - amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
24 - resets: phandles to the reset lines needed for this power demain sequence
26 - clocks: from common clock binding: handle to VPU and VAPB clocks
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dimg-mdc-dma.txt1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #address-cells = <1>;
6 #size-cells = <1>;
10 #address-cells = <1>;
11 #size-cells = <0>;
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
[all …]

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