Searched full:sdrams (Results 1 – 6 of 6) sorted by relevance
206 * the SDRAMs within their permissible period. The refresh period is256 * The clock could be going away for some time. Set the SDRAMs in sa1110_target()
18 for DDR3L and LPDDR3 SDRAMs.
35 SDRAMs.
4 asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
60 * 01=7.8usec (256Mbit SDRAMs)
1893 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M10()2125 /* Full reset sdrams, this also re-inits the MDLL */ in radeon_reinitialize_M9P()